#include <HexagonISelLowering.h>

Inheritance diagram for llvm::HexagonTargetLowering:

Collaboration diagram for llvm::HexagonTargetLowering:

Public Member Functions
	HexagonTargetLowering (HexagonTargetMachine &targetmachine)

bool	IsEligibleForTailCallOptimization (SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const

virtual bool	isTruncateFree (Type Ty1, Type Ty2) const

virtual bool	isTruncateFree (EVT VT1, EVT VT2) const

virtual bool	allowTruncateForTailCall (Type Ty1, Type Ty2) const

virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const

virtual const char *	getTargetNodeName (unsigned Opcode) const
	This method returns the name of a target specific DAG node. More...

SDValue	LowerBR_JT (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerDYNAMIC_STACKALLOC (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerINLINEASM (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerEH_LABEL (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerEH_RETURN (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const

SDValue	LowerGLOBALADDRESS (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerBlockAddress (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerCall (TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const

SDValue	LowerCallResult (SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const

SDValue	LowerSELECT_CC (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerFRAMEADDR (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerRETURNADDR (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const

virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr MI, MachineBasicBlock BB) const

SDValue	LowerVASTART (SDValue Op, SelectionDAG &DAG) const

SDValue	LowerConstantPool (SDValue Op, SelectionDAG &DAG) const

virtual EVT	getSetCCResultType (LLVMContext &C, EVT VT) const

virtual bool	getPostIndexedAddressParts (SDNode N, SDNode Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const

std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const

virtual SDValue	LowerINTRINSIC_WO_CHAIN (SDValue Op, SelectionDAG &DAG) const

virtual bool	isLegalAddressingMode (const AddrMode &AM, Type *Ty) const

virtual bool	isFPImmLegal (const APFloat &Imm, EVT VT) const

virtual bool	isLegalICmpImmediate (int64_t Imm) const

Public Member Functions inherited from llvm::TargetLowering
	TargetLowering (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual bool	getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const

virtual unsigned	getJumpTableEncoding () const

virtual const MCExpr *	LowerCustomJumpTableEntry (const MachineJumpTableInfo , const MachineBasicBlock , unsigned, MCContext &) const

virtual SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
	Returns relocation base for the given PIC jumptable. More...

virtual const MCExpr *	getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const

virtual bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const

bool	isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const

std::pair< SDValue, SDValue >	makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
	Returns a pair of (return value, chain). More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const

virtual void	computeMaskedBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const

virtual unsigned	ComputeNumSignBitsForTargetNode (SDValue Op, unsigned Depth=0) const

SDValue	SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const

virtual bool	isGAPlusOffset (SDNode N, const GlobalValue &GA, int64_t &Offset) const

virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const

virtual bool	isTypeDesirableForOp (unsigned, EVT VT) const

virtual bool	isDesirableToTransformToIntegerOp (unsigned, EVT) const

virtual bool	IsDesirableToPromoteOp (SDValue, EVT &) const

std::pair< SDValue, SDValue >	LowerCallTo (CallLoweringInfo &CLI) const

virtual void	HandleByVal (CCState *, unsigned &, unsigned) const
	Target-specific cleanup for formal ByVal parameters. More...

virtual bool	CanLowerReturn (CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const

virtual bool	isUsedByReturnOnly (SDNode *, SDValue &) const

virtual bool	mayBeEmittedAsTailCall (CallInst *) const

virtual MVT	getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const

virtual const uint16_t *	getScratchRegisters (CallingConv::ID CC) const

virtual void	LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const

virtual void	ReplaceNodeResults (SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const

virtual FastISel *	createFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const

virtual bool	ExpandInlineAsm (CallInst *) const

virtual AsmOperandInfoVector	ParseConstraints (ImmutableCallSite CS) const

virtual ConstraintWeight	getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const

virtual ConstraintWeight	getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const

virtual void	ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=0) const

virtual ConstraintType	getConstraintType (const std::string &Constraint) const
	Given a constraint, return the type of constraint it is for this target. More...

virtual const char *	LowerXConstraint (EVT ConstraintVT) const

virtual void	LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const

SDValue	BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
	Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...

SDValue	BuildSDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

SDValue	BuildUDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

virtual void	AdjustInstrPostInstrSelection (MachineInstr MI, SDNode Node) const

Public Member Functions inherited from llvm::TargetLoweringBase
	TargetLoweringBase (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual	~TargetLoweringBase ()

const TargetMachine &	getTargetMachine () const

const DataLayout *	getDataLayout () const

const TargetLoweringObjectFile &	getObjFileLowering () const

bool	isBigEndian () const

bool	isLittleEndian () const

virtual MVT	getPointerTy (uint32_t=0) const

unsigned	getPointerSizeInBits (uint32_t AS=0) const

unsigned	getPointerTypeSizeInBits (Type *Ty) const

virtual MVT	getScalarShiftAmountTy (EVT LHSTy) const

EVT	getShiftAmountTy (EVT LHSTy) const

virtual MVT	getVectorIdxTy () const

bool	isSelectExpensive () const
	Return true if the select operation is expensive for this target. More...

virtual bool	isSelectSupported (SelectSupportKind) const

virtual bool	shouldSplitVectorElementType (EVT) const

bool	isIntDivCheap () const

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed. More...

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const

bool	isPow2DivCheap () const
	Return true if pow2 div is cheaper than a chain of srl/add/sra. More...

bool	isJumpExpensive () const

bool	isPredictableSelectExpensive () const

virtual bool	isLoadBitCastBeneficial (EVT, EVT) const

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const

BooleanContent	getBooleanContents (bool isVec) const

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference. More...

virtual Sched::Preference	getSchedulingPreference (SDNode *) const

virtual const TargetRegisterClass *	getRegClassFor (MVT VT) const

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const

virtual uint8_t	getRepRegClassCostFor (MVT VT) const

bool	isTypeLegal (EVT VT) const

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const

LegalizeTypeAction	getTypeAction (MVT VT) const

EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

virtual bool	getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const

virtual bool	isShuffleMaskLegal (const SmallVectorImpl< int > &, EVT) const

virtual bool	canOpTrap (unsigned Op, EVT VT) const

virtual bool	isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT) const

bool	isOperationLegalOrPromote (unsigned Op, EVT VT) const

bool	isOperationExpand (unsigned Op, EVT VT) const

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target. More...

LegalizeAction	getLoadExtAction (unsigned ExtType, MVT VT) const

bool	isLoadExtLegal (unsigned ExtType, EVT VT) const
	Return true if the specified load with extension is legal on this target. More...

LegalizeAction	getTruncStoreAction (MVT ValVT, MVT MemVT) const

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal on this target. More...

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const

EVT	getValueType (Type *Ty, bool AllowUnknown=false) const

MVT	getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType. More...

virtual unsigned	getByValTypeAlignment (Type *Ty) const

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

unsigned	getNumRegisters (LLVMContext &Context, EVT VT) const

virtual bool	ShouldShrinkFPConstant (EVT) const

bool	hasTargetDAGCombine (ISD::NodeType NT) const

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset. More...

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy. More...

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove. More...

virtual bool	allowsUnalignedMemoryAccesses (EVT, bool *=0) const
	Determine if the target supports unaligned memory accesses. More...

virtual EVT	getOptimalMemOpType (uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const

virtual bool	isSafeMemOpType (MVT) const

bool	usesUnderscoreSetJmp () const
	Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...

bool	usesUnderscoreLongJmp () const
	Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...

bool	supportJumpTables () const
	Return whether the target can generate code for jump tables. More...

int	getMinimumJumpTableEntries () const

unsigned	getStackPointerRegisterToSaveRestore () const

unsigned	getExceptionPointerRegister () const

unsigned	getExceptionSelectorRegister () const

unsigned	getJumpBufSize () const

unsigned	getJumpBufAlignment () const

unsigned	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument. More...

unsigned	getMinFunctionAlignment () const
	Return the minimum function alignment. More...

unsigned	getPrefFunctionAlignment () const
	Return the preferred function alignment. More...

unsigned	getPrefLoopAlignment () const
	Return the preferred loop alignment. More...

bool	getInsertFencesForAtomic () const

virtual bool	getStackCookieLocation (unsigned &, unsigned &) const

virtual unsigned	getMaximalGlobalOffset () const

virtual bool	isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast between SrcAS and DestAS is a noop. More...

virtual void	resetOperationActions ()
	Reset the operation actions based on target options. More...

virtual bool	GetAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const

virtual int	getScalingFactorCost (const AddrMode &AM, Type *Ty) const
	Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...

virtual bool	isLegalAddImmediate (int64_t) const

virtual bool	isZExtFree (Type , Type ) const

virtual bool	isZExtFree (EVT, EVT) const

virtual bool	hasPairedLoad (Type *, unsigned &) const

virtual bool	hasPairedLoad (EVT, unsigned &) const

virtual bool	isZExtFree (SDValue Val, EVT VT2) const

virtual bool	isFNegFree (EVT VT) const

virtual bool	isFAbsFree (EVT VT) const

virtual bool	isFMAFasterThanFMulAndFAdd (EVT) const

virtual bool	isNarrowingProfitable (EVT, EVT) const

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall. More...

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall. More...

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall. More...

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall. More...

LegalizeKind	getTypeConversion (LLVMContext &Context, EVT VT) const

int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode. More...

std::pair< unsigned, MVT >	getTypeLegalizationCost (Type *Ty) const
	Estimate the cost of type-legalization and the legalized type. More...

Public Attributes
HexagonTargetMachine &	TM

Additional Inherited Members
Public Types inherited from llvm::TargetLowering
enum	ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown }

enum	ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay }

typedef std::vector< ArgListEntry >	ArgListTy

typedef std::vector < AsmOperandInfo >	AsmOperandInfoVector

Public Types inherited from llvm::TargetLoweringBase
enum	LegalizeAction { Legal, Promote, Expand, Custom }

enum	LegalizeTypeAction { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector }

enum	BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

typedef std::pair < LegalizeTypeAction, EVT >	LegalizeKind

Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Member Functions inherited from llvm::TargetLoweringBase
void	initActions ()
	Initialize all of the actions to default values. More...

void	setBooleanContents (BooleanContent Ty)

void	setBooleanVectorContents (BooleanContent Ty)

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference. More...

void	setUseUnderscoreSetJmp (bool Val)

void	setUseUnderscoreLongJmp (bool Val)

void	setSupportJumpTables (bool Val)
	Indicate whether the target can generate code for jump tables. More...

void	setMinimumJumpTableEntries (int Val)

void	setStackPointerRegisterToSaveRestore (unsigned R)

void	setExceptionPointerRegister (unsigned R)

void	setExceptionSelectorRegister (unsigned R)

void	setSelectIsExpensive (bool isExpensive=true)

void	setJumpIsExpensive (bool isExpensive=true)

void	setIntDivIsCheap (bool isCheap=true)

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass. More...

void	setPow2DivIsCheap (bool isCheap=true)

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)

void	clearRegisterClasses ()
	Remove all register classes. More...

void	clearOperationActions ()
	Remove all operation actions. More...

virtual std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (MVT VT) const

void	computeRegisterProperties ()

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)

void	setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)

void	setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)

void	setTargetDAGCombine (ISD::NodeType NT)

void	setJumpBufSize (unsigned Size)
	Set the target's required jmp_buf buffer size (in bytes); default is 200. More...

void	setJumpBufAlignment (unsigned Align)

void	setMinFunctionAlignment (unsigned Align)
	Set the target's minimum function alignment (in log2(bytes)) More...

void	setPrefFunctionAlignment (unsigned Align)

void	setPrefLoopAlignment (unsigned Align)

void	setMinStackArgumentAlignment (unsigned Align)
	Set the minimum stack alignment of an argument (in log2(bytes)). More...

void	setInsertFencesForAtomic (bool fence)

bool	isLegalRC (const TargetRegisterClass *RC) const

Protected Attributes inherited from llvm::TargetLoweringBase
unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call. More...

unsigned	MaxStoresPerMemsetOptSize

unsigned	MaxStoresPerMemcpy
	Specify maximum bytes of store instructions per memcpy call. More...

unsigned	MaxStoresPerMemcpyOptSize

unsigned	MaxStoresPerMemmove
	Specify maximum bytes of store instructions per memmove call. More...

unsigned	MaxStoresPerMemmoveOptSize

bool	PredictableSelectIsExpensive

Detailed Description

Definition at line 70 of file HexagonISelLowering.h.

Constructor & Destructor Documentation

HexagonTargetLowering::HexagonTargetLowering ( HexagonTargetMachine & targetmachine )

explicit

Definition at line 1054 of file HexagonISelLowering.cpp.

Member Function Documentation

bool HexagonTargetLowering::allowTruncateForTailCall	(	Type *	,
		Type *
	)		const

virtual

Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1521 of file HexagonISelLowering.cpp.

References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().

MachineBasicBlock * HexagonTargetLowering::EmitInstrWithCustomInserter	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB
	)		const

virtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow.

Reimplemented from llvm::TargetLowering.

Definition at line 1592 of file HexagonISelLowering.cpp.

References llvm::HexagonMachineFunctionInfo::addAllocaAdjustInst(), llvm::HexagonISD::ADJDYNALLOC, llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), and llvm_unreachable.

bool HexagonTargetLowering::getPostIndexedAddressParts	(	SDNode *	N,
		SDNode *	Op,
		SDValue &	Base,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG
	)		const

virtual

getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented from llvm::TargetLowering.

Definition at line 652 of file HexagonISelLowering.cpp.

References getIndexedAddressParts(), llvm::SDValue::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::i64, Is_PostInc_S4_Offset(), llvm::ISD::isSEXTLoad(), llvm::A64DB::LD, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::ISD::SEXTLOAD, and llvm::A64DB::ST.

std::pair< unsigned, const TargetRegisterClass * > HexagonTargetLowering::getRegForInlineAsmConstraint	(	const std::string &	Constraint,
		MVT	VT
	)		const

virtual

Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer..

Reimplemented from llvm::TargetLowering.

Definition at line 1612 of file HexagonISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, and llvm::MVT::SimpleTy.

virtual EVT llvm::HexagonTargetLowering::getSetCCResultType	(	LLVMContext &	Context,
		EVT	VT
	)		const

inlinevirtual

Return the ValueType of the result of SETCC operations. Also used to obtain the target's preferred type for the condition operand of SELECT and BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other since there are no other operands to get a type hint from.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 144 of file HexagonISelLowering.h.

References llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i1, and llvm::EVT::isVector().

const char * HexagonTargetLowering::getTargetNodeName ( unsigned Opcode ) const

virtual

This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 1478 of file HexagonISelLowering.cpp.

bool HexagonTargetLowering::IsEligibleForTailCallOptimization	(	SDValue	Callee,
		CallingConv::ID	CalleeCC,
		bool	isVarArg,
		bool	isCalleeStructRet,
		bool	isCallerStructRet,
		const SmallVectorImpl< ISD::OutputArg > &	Outs,
		const SmallVectorImpl< SDValue > &	OutVals,
		const SmallVectorImpl< ISD::InputArg > &	Ins,
		SelectionDAG &	DAG
	)		const

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Targets which want to do tail call optimization should implement this function.

Definition at line 1682 of file HexagonISelLowering.cpp.

References llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::SelectionDAG::getMachineFunction().

Referenced by LowerCall().

bool HexagonTargetLowering::isFPImmLegal	(	const APFloat &	Imm,
		EVT	VT
	)		const

virtual

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1641 of file HexagonISelLowering.cpp.

References llvm::HexagonTargetMachine::getRegisterInfo(), llvm::HexagonSubtarget::hasV5TOps(), llvm::HexagonRegisterInfo::Subtarget, and TM.

bool HexagonTargetLowering::isLegalAddressingMode	(	const AddrMode &	AM,
		Type *	Ty
	)		const

virtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1648 of file HexagonISelLowering.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, and llvm::TargetLoweringBase::AddrMode::Scale.

bool HexagonTargetLowering::isLegalICmpImmediate ( int64_t Imm ) const

virtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1675 of file HexagonISelLowering.cpp.

bool HexagonTargetLowering::isTruncateFree	(	Type *	,
		Type *
	)		const

virtual

Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1504 of file HexagonISelLowering.cpp.

References llvm::EVT::getEVT(), llvm::EVT::getSimpleVT(), llvm::MVT::i32, llvm::MVT::i64, and llvm::EVT::isSimple().

bool HexagonTargetLowering::isTruncateFree	(	EVT	VT1,
		EVT	VT2
	)		const

virtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1513 of file HexagonISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::MVT::i32, llvm::MVT::i64, and llvm::EVT::isSimple().

SDValue HexagonTargetLowering::LowerATOMIC_FENCE	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 1018 of file HexagonISelLowering.cpp.

References llvm::HexagonISD::BARRIER, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), and llvm::MVT::Other.

Referenced by LowerOperation().

SDValue HexagonTargetLowering::LowerBlockAddress	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 1043 of file HexagonISelLowering.cpp.

References llvm::HexagonISD::CONST32_GP, llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetBlockAddress(), and llvm::MVT::i32.

Referenced by LowerOperation().

SDValue HexagonTargetLowering::LowerBR_JT	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

SDValue HexagonTargetLowering::LowerCall	(	TargetLowering::CallLoweringInfo &	CLI,
		SmallVectorImpl< SDValue > &	InVals
	)		const

virtual

LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.

Reimplemented from llvm::TargetLowering.

Definition at line 394 of file HexagonISelLowering.cpp.

SDValue HexagonTargetLowering::LowerCallResult	(	SDValue	Chain,
		SDValue	InFlag,
		CallingConv::ID	CallConv,
		bool	isVarArg,
		const SmallVectorImpl< ISD::InputArg > &	Ins,
		SDLoc	dl,
		SelectionDAG &	DAG,
		SmallVectorImpl< SDValue > &	InVals,
		const SmallVectorImpl< SDValue > &	OutVals,
		SDValue	Callee
	)		const

LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropriate physical registers. This assumes that Chain/InFlag are the input chain/flag to use, and that TheCall is the call being lowered. Returns a SDNode with the same number of values as the ISD::CALL.

Definition at line 362 of file HexagonISelLowering.cpp.

References llvm::CCState::AnalyzeCallResult(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValue(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), RetCC_Hexagon(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by LowerCall().

SDValue HexagonTargetLowering::LowerConstantPool	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 963 of file HexagonISelLowering.cpp.

References llvm::HexagonISD::CONST32, llvm::ConstantPoolSDNode::getAlignment(), llvm::ConstantPoolSDNode::getConstVal(), llvm::ConstantPoolSDNode::getMachineCPVal(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SDValue::getValueType(), and llvm::ConstantPoolSDNode::isMachineConstantPoolEntry().

Referenced by LowerOperation().

SDValue HexagonTargetLowering::LowerDYNAMIC_STACKALLOC	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 779 of file HexagonISelLowering.cpp.

References llvm::HexagonISD::ADJDYNALLOC, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::HexagonTargetMachine::getRegisterInfo(), llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore(), llvm::HexagonRegisterInfo::getStackRegister(), llvm::MVT::i32, llvm::ISD::SUB, and TM.

Referenced by LowerOperation().

SDValue llvm::HexagonTargetLowering::LowerEH_LABEL	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

SDValue HexagonTargetLowering::LowerEH_RETURN	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 1534 of file HexagonISelLowering.cpp.

References llvm::ISD::ADD, llvm::HexagonISD::EH_RETURN, llvm::SelectionDAG::getCopyToReg(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::MVT::Other, and llvm::HexagonMachineFunctionInfo::setHasEHReturn().

Referenced by LowerOperation().

SDValue HexagonTargetLowering::LowerFormalArguments	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::InputArg > &	,
		SDLoc	,
		SelectionDAG &	,
		SmallVectorImpl< SDValue > &
	)		const

virtual

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.

Reimplemented from llvm::TargetLowering.

Definition at line 824 of file HexagonISelLowering.cpp.

References llvm::MachineRegisterInfo::addLiveIn(), llvm::CCState::AnalyzeFormalArguments(), CC_Hexagon(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SmallVectorBase::empty(), llvm::MVT::f32, llvm::ISD::FrameIndex, llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::MVT::getStoreSizeInBits(), llvm::TargetLoweringBase::getTargetMachine(), HEXAGON_LRFP_SIZE, Hexagon_PointerSize, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::ArgFlagsTy::isByVal(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::HexagonMachineFunctionInfo::setVarArgsFrameIndex(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::ISD::TokenFactor.

SDValue HexagonTargetLowering::LowerFRAMEADDR	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 1001 of file HexagonISelLowering.cpp.

References llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getFrameInfo(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getOperand(), llvm::HexagonTargetMachine::getRegisterInfo(), llvm::SDValue::getValueType(), llvm::MachineFrameInfo::setFrameAddressIsTaken(), and TM.

Referenced by LowerOperation(), and LowerRETURNADDR().

SDValue HexagonTargetLowering::LowerGLOBALADDRESS	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 1025 of file HexagonISelLowering.cpp.

References llvm::HexagonISD::CONST32, llvm::HexagonISD::CONST32_GP, llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getObjFileLowering(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), and llvm::HexagonTargetObjectFile::IsGlobalInSmallSection().

Referenced by LowerOperation().

SDValue HexagonTargetLowering::LowerINLINEASM	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

SDValue HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

virtual

Definition at line 287 of file HexagonISelLowering.cpp.

Referenced by LowerOperation().

SDValue HexagonTargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

virtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented from llvm::TargetLowering.

Definition at line 1561 of file HexagonISelLowering.cpp.

References llvm::ISD::ATOMIC_FENCE, llvm::ISD::BlockAddress, llvm::ISD::BR_JT, llvm::ISD::ConstantPool, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_RETURN, llvm::ISD::FRAMEADDR, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INLINEASM, llvm::ISD::INTRINSIC_WO_CHAIN, llvm_unreachable, LowerATOMIC_FENCE(), LowerBlockAddress(), LowerBR_JT(), LowerConstantPool(), LowerDYNAMIC_STACKALLOC(), LowerEH_RETURN(), LowerFRAMEADDR(), LowerGLOBALADDRESS(), LowerINLINEASM(), LowerINTRINSIC_WO_CHAIN(), LowerRETURNADDR(), LowerSELECT_CC(), LowerVASTART(), llvm::ISD::RETURNADDR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, and llvm::ISD::VASTART.

SDValue HexagonTargetLowering::LowerReturn	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::OutputArg > &	,
		const SmallVectorImpl< SDValue > &	,
		SDLoc	,
		SelectionDAG &
	)		const

virtual

This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. The implementation should return the resulting token chain value.

Reimplemented from llvm::TargetLowering.

Definition at line 313 of file HexagonISelLowering.cpp.

References llvm::CCState::AnalyzeReturn(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyToReg(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValue(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::HexagonISD::RET_FLAG, RetCC_Hexagon(), and llvm::SmallVectorTemplateCommon< T >::size().