#include <X86InstrInfo.h>

Inheritance diagram for llvm::X86InstrInfo:

Collaboration diagram for llvm::X86InstrInfo:

Public Member Functions
	X86InstrInfo (X86TargetMachine &tm)

virtual const X86RegisterInfo &	getRegisterInfo () const

virtual bool	isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const

unsigned	isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const

unsigned	isLoadFromStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const

unsigned	isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const

unsigned	isStoreToStackSlotPostFE (const MachineInstr *MI, int &FrameIndex) const

bool	isReallyTriviallyReMaterializable (const MachineInstr MI, AliasAnalysis AA) const

void	reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const

bool	classifyLEAReg (MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const

virtual MachineInstr *	convertToThreeAddress (MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const

virtual MachineInstr *	commuteInstruction (MachineInstr *MI, bool NewMI) const

virtual bool	isUnpredicatedTerminator (const MachineInstr *MI) const

virtual bool	AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const

virtual unsigned	RemoveBranch (MachineBasicBlock &MBB) const

virtual unsigned	InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const

virtual bool	canInsertSelect (const MachineBasicBlock &, const SmallVectorImpl< MachineOperand > &Cond, unsigned, unsigned, int &, int &, int &) const

virtual void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const

virtual void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const

virtual void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const

virtual void	storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr > &NewMIs) const

virtual void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const

virtual void	loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr > &NewMIs) const

virtual bool	expandPostRAPseudo (MachineBasicBlock::iterator MI) const

virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const

virtual MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr LoadMI) const

virtual bool	canFoldMemoryOperand (const MachineInstr *, const SmallVectorImpl< unsigned > &) const

virtual bool	unfoldMemoryOperand (MachineFunction &MF, MachineInstr MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr > &NewMIs) const

virtual bool	unfoldMemoryOperand (SelectionDAG &DAG, SDNode N, SmallVectorImpl< SDNode > &NewNodes) const

virtual unsigned	getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=0) const

virtual bool	areLoadsFromSameBasePtr (SDNode Load1, SDNode Load2, int64_t &Offset1, int64_t &Offset2) const

virtual bool	shouldScheduleLoadsNear (SDNode Load1, SDNode Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const

virtual bool	shouldScheduleAdjacent (MachineInstr First, MachineInstr Second) const LLVM_OVERRIDE

virtual void	getNoopForMachoTarget (MCInst &NopInst) const
	getNoopForMachoTarget - Return the noop instruction to use for a noop. More...

virtual bool	ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const

bool	isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const

unsigned	getGlobalBaseReg (MachineFunction *MF) const

std::pair< uint16_t, uint16_t >	getExecutionDomain (const MachineInstr *MI) const

void	setExecutionDomain (MachineInstr *MI, unsigned Domain) const

unsigned	getPartialRegUpdateClearance (const MachineInstr MI, unsigned OpNum, const TargetRegisterInfo TRI) const

unsigned	getUndefRegClearance (const MachineInstr MI, unsigned &OpNum, const TargetRegisterInfo TRI) const

void	breakPartialRegDependency (MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const

MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, unsigned OpNum, const SmallVectorImpl< MachineOperand > &MOs, unsigned Size, unsigned Alignment) const

bool	isHighLatencyDef (int opc) const

bool	hasHighOperandLatency (const InstrItineraryData ItinData, const MachineRegisterInfo MRI, const MachineInstr DefMI, unsigned DefIdx, const MachineInstr UseMI, unsigned UseIdx) const

virtual bool	analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const

virtual bool	optimizeCompareInstr (MachineInstr CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo MRI) const

virtual MachineInstr *	optimizeLoadInstr (MachineInstr MI, const MachineRegisterInfo MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const

Static Public Member Functions
static bool	isX86_64ExtendedReg (const MachineOperand &MO)

Detailed Description

Definition at line 130 of file X86InstrInfo.h.

Constructor & Destructor Documentation

X86InstrInfo::X86InstrInfo ( X86TargetMachine & tm )

explicit

Definition at line 98 of file X86InstrInfo.cpp.

References llvm::array_lengthof(), X86OpTblEntry::Flags, X86OpTblEntry::MemOp, X86OpTblEntry::RegOp, TB_ALIGN_16, TB_ALIGN_32, TB_ALIGN_64, TB_FOLDED_LOAD, TB_FOLDED_STORE, TB_INDEX_0, TB_INDEX_1, TB_INDEX_2, TB_INDEX_3, and TB_NO_REVERSE.

Member Function Documentation

bool X86InstrInfo::AnalyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify
	)		const

virtual

Definition at line 2707 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::SmallVectorImpl< T >::clear(), llvm::X86::COND_E, llvm::X86::COND_INVALID, llvm::X86::COND_NE, llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP, llvm::X86::COND_NP_OR_E, llvm::X86::COND_P, llvm::MachineOperand::CreateImm(), llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::eraseFromParent(), llvm::MachineInstr::eraseFromParent(), llvm::MachineBasicBlock::findDebugLoc(), GetCondBranchFromCond(), getCondFromBranchOpc(), GetOppositeBranchCondition(), I, llvm::MachineBasicBlock::isLayoutSuccessor(), isUnpredicatedTerminator(), llvm::next(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::SmallVectorTemplateCommon< T >::size().

bool X86InstrInfo::analyzeCompare	(	const MachineInstr *	MI,
		unsigned &	SrcReg,
		unsigned &	SrcReg2,
		int &	CmpMask,
		int &	CmpValue
	)		const

virtual

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.

Definition at line 3286 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool X86InstrInfo::areLoadsFromSameBasePtr	(	SDNode *	Load1,
		SDNode *	Load2,
		int64_t &	Offset1,
		int64_t &	Offset2
	)		const

virtual

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.

Definition at line 4761 of file X86InstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), and llvm::SDNode::isMachineOpcode().

void X86InstrInfo::breakPartialRegDependency	(	MachineBasicBlock::iterator	MI,
		unsigned	OpNum,
		const TargetRegisterInfo *	TRI
	)		const

Definition at line 4176 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), llvm::MCRegisterInfo::getSubReg(), llvm::TargetMachine::getSubtarget(), llvm::RegState::ImplicitDefine, llvm::A64CC::MI, and llvm::RegState::Undef.

bool X86InstrInfo::canFoldMemoryOperand	(	const MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops
	)		const

virtual

canFoldMemoryOperand - Returns true if the specified load / store is folding is possible.

Definition at line 4456 of file X86InstrInfo.cpp.

References llvm::TargetInstrInfo::canFoldMemoryOperand(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::count(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getTargetFlags(), llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, NoFusing, llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::MCOI::TIED_TO.

bool X86InstrInfo::canInsertSelect	(	const MachineBasicBlock &	MBB,
		const SmallVectorImpl< MachineOperand > &	Cond,
		unsigned	TrueReg,
		unsigned	FalseReg,
		int &	CondCycles,
		int &	TrueCycles,
		int &	FalseCycles
	)		const

virtual

Definition at line 2921 of file X86InstrInfo.cpp.

References llvm::X86::COND_S, llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::hasCMov(), MRI, and llvm::SmallVectorTemplateCommon< T >::size().

bool X86InstrInfo::classifyLEAReg	(	MachineInstr *	MI,
		const MachineOperand &	Src,
		unsigned	LEAOpcode,
		bool	AllowSP,
		unsigned &	NewSrc,
		bool &	isKill,
		bool &	isUndef,
		MachineOperand &	ImplicitOp
	)		const

Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.

Reference parameters are set to indicate how caller should add this operand to the LEA instruction.

Definition at line 1850 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetOpcode::COPY, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::getX86SubSuperRegister(), llvm::MVT::i64, llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::killsRegister(), llvm::MachineBasicBlock::LQR_Live, llvm::MachineBasicBlock::LQR_Unknown, llvm::A64CC::MI, llvm::MachineOperand::setImplicit(), and llvm::RegState::Undef.

Referenced by convertToThreeAddress().

MachineInstr * X86InstrInfo::commuteInstruction	(	MachineInstr *	MI,
		bool	NewMI
	)		const

virtual

commuteInstruction - We have a few instructions that must be hacked on to commute them.

Definition at line 2345 of file X86InstrInfo.cpp.

References llvm::MachineFunction::CloneMachineInstr(), llvm::TargetInstrInfo::commuteInstruction(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm_unreachable, llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setImm().

Referenced by optimizeLoadInstr().

MachineInstr * X86InstrInfo::convertToThreeAddress	(	MachineFunction::iterator &	MFI,
		MachineBasicBlock::iterator &	MBBI,
		LiveVariables *	LV
	)		const

virtual

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.

This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.

Definition at line 2044 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), llvm::BuildMI(), llvm::CallingConv::C, classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getSubtarget(), getTruncatedShiftCount(), llvm::getUndefRegState(), hasLiveCondCodeDef(), llvm::X86Subtarget::hasSSE2(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), isTruncatedShiftCountForLEA(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::A64CC::MI, and llvm::LiveVariables::replaceKillInstruction().

void X86InstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		DebugLoc	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc
	)		const

virtual

Definition at line 3035 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), copyPhysRegOpcode_AVX512(), CopyToFromAsymmetricReg(), llvm::dbgs(), DEBUG, llvm::getKillRegState(), llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::is64Bit(), isHReg(), and llvm_unreachable.

bool X86InstrInfo::expandPostRAPseudo ( MachineBasicBlock::iterator MI ) const

virtual

Definition at line 3836 of file X86InstrInfo.cpp.

References Expand2AddrUndef(), llvm::TargetMachine::getSubtarget(), and llvm::A64CC::MI.

MachineInstr * X86InstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops,
		int	FrameIndex
	)		const

virtual

foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.

Definition at line 4262 of file X86InstrInfo.cpp.

References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateFI(), foldPatchpoint(), llvm::Function::getAttributes(), llvm::MachineFunction::getFrameInfo(), llvm::X86TargetMachine::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetFrameLowering::getStackAlignment(), hasPartialRegUpdate(), llvm::X86RegisterInfo::needsStackRealignment(), NoFusing, llvm::Attribute::OptimizeForSize, llvm::TargetOpcode::PATCHPOINT, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::TargetOpcode::STACKMAP.

Referenced by foldMemoryOperandImpl().

MachineInstr * X86InstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops,
		MachineInstr *	LoadMI
	)		const

virtual

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.

Definition at line 4312 of file X86InstrInfo.cpp.

References llvm::X86::AddrNumOperands, llvm::CallingConv::C, llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::ISD::FrameIndex, llvm::VectorType::get(), llvm::Constant::getAllOnesValue(), llvm::Function::getAttributes(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getRelocationModel(), llvm::MachineOperand::getSubReg(), llvm::TargetMachine::getSubtarget(), llvm::MachineInstr::hasOneMemOperand(), hasPartialRegUpdate(), llvm::X86Subtarget::is64Bit(), isLoadFromStackSlot(), llvm::CodeModel::Kernel, llvm::MachineInstr::memoperands_begin(), NoFusing, llvm::Attribute::OptimizeForSize, llvm::Reloc::PIC_, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::CodeModel::Small.

MachineInstr * X86InstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		unsigned	OpNum,
		const SmallVectorImpl< MachineOperand > &	MOs,
		unsigned	Size,
		unsigned	Alignment
	)		const

Definition at line 3939 of file X86InstrInfo.cpp.

References llvm::dbgs(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::find(), FuseInst(), FuseTwoAddrInst(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::TargetMachine::getSubtarget(), llvm::MachineOperand::getTargetFlags(), I, llvm::MachineInstr::isCopy(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), MakeM0Inst(), llvm::A64CC::MI, llvm::MinAlign(), llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, PrintFailedFusing, llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), TB_ALIGN_MASK, TB_ALIGN_SHIFT, and llvm::MCOI::TIED_TO.

std::pair< uint16_t, uint16_t > X86InstrInfo::getExecutionDomain ( const MachineInstr * MI ) const

Definition at line 5196 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::TargetMachine::getSubtarget(), lookup(), lookupAVX2(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.

unsigned X86InstrInfo::getGlobalBaseReg ( MachineFunction * MF ) const

getGlobalBaseReg - Return a virtual register initialized with the the global base register value. Output instructions required to initialize the register in the function entry block, if necessary.

TODO: Eliminate this and move the code to X86MachineFunctionInfo.

Definition at line 5100 of file X86InstrInfo.cpp.

References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::TargetMachine::getSubtarget(), llvm::PPCISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().

void X86InstrInfo::getNoopForMachoTarget ( MCInst & NopInst ) const

virtual

getNoopForMachoTarget - Return the noop instruction to use for a noop.

Definition at line 5222 of file X86InstrInfo.cpp.

References llvm::MCInst::setOpcode().

unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold	(	unsigned	Opc,
		bool	UnfoldLoad,
		bool	UnfoldStore,
		unsigned *	LoadRegIndex = `0`
	)		const

virtual

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.

Definition at line 4742 of file X86InstrInfo.cpp.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::find(), I, TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.

unsigned X86InstrInfo::getPartialRegUpdateClearance	(	const MachineInstr *	MI,
		unsigned	OpNum,
		const TargetRegisterInfo *	TRI
	)		const

getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update.

Definition at line 4089 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasPartialRegUpdate(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineOperand::readsReg(), llvm::MachineInstr::readsRegister(), and llvm::MachineInstr::readsVirtualRegister().

virtual const X86RegisterInfo& llvm::X86InstrInfo::getRegisterInfo ( ) const

inlinevirtual

getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 164 of file X86InstrInfo.h.

Referenced by classifyLEAReg(), llvm::X86TargetMachine::getRegisterInfo(), and optimizeCompareInstr().

unsigned X86InstrInfo::getUndefRegClearance	(	const MachineInstr *	MI,
		unsigned &	OpNum,
		const TargetRegisterInfo *	TRI
	)		const

Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register reads.

This catches the VCVTSI2SD family of instructions:

vcvtsi2sdq rax, xmm0<undef>, xmm14

We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:

vxorps xmm1<undef>, xmm1<undef>, xmm1

Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.

Definition at line 4159 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineOperand::isUndef().

bool X86InstrInfo::hasHighOperandLatency	(	const InstrItineraryData *	ItinData,
		const MachineRegisterInfo *	MRI,
		const MachineInstr *	DefMI,
		unsigned	DefIdx,
		const MachineInstr *	UseMI,
		unsigned	UseIdx
	)		const

Definition at line 5304 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isHighLatencyDef().

unsigned X86InstrInfo::InsertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		const SmallVectorImpl< MachineOperand > &	Cond,
		DebugLoc	DL
	)		const

virtual

Definition at line 2872 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::BuildMI(), llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP_OR_E, llvm::SmallVectorBase::empty(), GetCondBranchFromCond(), and llvm::SmallVectorTemplateCommon< T >::size().

void X86InstrInfo::insertSelect	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		DebugLoc	DL,
		unsigned	DstReg,
		const SmallVectorImpl< MachineOperand > &	Cond,
		unsigned	TrueReg,
		unsigned	FalseReg
	)		const

virtual

Definition at line 2957 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), getCMovFromCond(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), MRI, and llvm::SmallVectorTemplateCommon< T >::size().

bool X86InstrInfo::isCoalescableExtInstr	(	const MachineInstr &	MI,
		unsigned &	SrcReg,
		unsigned &	DstReg,
		unsigned &	SubIdx
	)		const

virtual

isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.

Definition at line 1453 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::is64Bit(), and llvm_unreachable.

bool X86InstrInfo::isHighLatencyDef ( int opc ) const

Definition at line 5226 of file X86InstrInfo.cpp.

Referenced by hasHighOperandLatency().

unsigned X86InstrInfo::isLoadFromStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const

Definition at line 1574 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameLoadOpcode().

Referenced by foldMemoryOperandImpl(), isLoadFromStackSlotPostFE(), and MatchingStackOffset().

unsigned X86InstrInfo::isLoadFromStackSlotPostFE	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness.

Definition at line 1582 of file X86InstrInfo.cpp.

References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameLoadOpcode(), and isLoadFromStackSlot().

bool X86InstrInfo::isReallyTriviallyReMaterializable	(	const MachineInstr *	MI,
		AliasAnalysis *	AA
	)		const

Definition at line 1636 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isInvariantLoad(), llvm::MachineOperand::isReg(), MRI, regIsPICBase(), and ReMatPICStubLoad.

bool X86InstrInfo::isSafeToMoveRegClassDefs ( const TargetRegisterClass * RC ) const

isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.

Definition at line 5087 of file X86InstrInfo.cpp.

unsigned X86InstrInfo::isStoreToStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const

Definition at line 1595 of file X86InstrInfo.cpp.

References llvm::X86::AddrNumOperands, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameStoreOpcode().

Referenced by isStoreToStackSlotPostFE().

unsigned X86InstrInfo::isStoreToStackSlotPostFE	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness.

Definition at line 1604 of file X86InstrInfo.cpp.

References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameStoreOpcode(), and isStoreToStackSlot().

bool X86InstrInfo::isUnpredicatedTerminator ( const MachineInstr * MI ) const

virtual

Definition at line 2696 of file X86InstrInfo.cpp.

References llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isPredicable(), and llvm::MachineInstr::isTerminator().

Referenced by AnalyzeBranch().

static bool llvm::X86InstrInfo::isX86_64ExtendedReg ( const MachineOperand & MO )

inlinestatic

Definition at line 356 of file X86InstrInfo.h.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), and llvm::X86II::isX86_64ExtendedReg().

Referenced by determineREX().

void X86InstrInfo::loadRegFromAddr	(	MachineFunction &	MF,
		unsigned	DestReg,
		SmallVectorImpl< MachineOperand > &	Addr,
		const TargetRegisterClass *	RC,
		MachineInstr::mmo_iterator	MMOBegin,
		MachineInstr::mmo_iterator	MMOEnd,
		SmallVectorImpl< MachineInstr * > &	NewMIs
	)		const

virtual

Definition at line 3267 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineMemOperand::getAlignment(), getLoadRegOpcode(), llvm::TargetRegisterClass::getSize(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by unfoldMemoryOperand().

void X86InstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

virtual

Definition at line 3253 of file X86InstrInfo.cpp.

References llvm::addFrameReference(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::MachineBasicBlock::findDebugLoc(), llvm::X86TargetMachine::getFrameLowering(), getLoadRegOpcode(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), and llvm::TargetFrameLowering::getStackAlignment().

bool X86InstrInfo::optimizeCompareInstr	(	MachineInstr *	CmpInstr,
		unsigned	SrcReg,
		unsigned	SrcReg2,
		int	CmpMask,
		int	CmpValue,
		const MachineRegisterInfo *	MRI
	)		const

virtual

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.

Definition at line 3492 of file X86InstrInfo.cpp.

MachineInstr * X86InstrInfo::optimizeLoadInstr	(	MachineInstr *	MI,
		const MachineRegisterInfo *	MRI,
		unsigned &	FoldAsLoadDefReg,
		MachineInstr *&	DefMI
	)		const

virtual

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.

Definition at line 3744 of file X86InstrInfo.cpp.

References commuteInstruction(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isCommutable(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), llvm::MachineInstr::mayLoad(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and SawStore.

void X86InstrInfo::reMaterialize	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	DestReg,
		unsigned	SubIdx,
		const MachineInstr *	Orig,
		const TargetRegisterInfo &	TRI
	)		const

Definition at line 1795 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), isSafeToClobberEFLAGS(), llvm::prior(), and llvm::MachineInstr::substituteRegister().

unsigned X86InstrInfo::RemoveBranch ( MachineBasicBlock & MBB ) const

virtual

Definition at line 2851 of file X86InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::X86::COND_INVALID, llvm::MachineBasicBlock::end(), getCondFromBranchOpc(), and I.

bool X86InstrInfo::ReverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

virtual

Definition at line 5077 of file X86InstrInfo.cpp.

References llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP_OR_E, GetOppositeBranchCondition(), and llvm::SmallVectorTemplateCommon< T >::size().

void X86InstrInfo::setExecutionDomain	(	MachineInstr *	MI,
		unsigned	Domain
	)		const

Definition at line 5207 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::hasAVX2(), lookup(), lookupAVX2(), llvm::MachineInstr::setDesc(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.

bool X86InstrInfo::shouldScheduleAdjacent	(	MachineInstr *	First,
		MachineInstr *	Second
	)		const

virtual

Definition at line 4914 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::TargetMachine::getSubtarget(), and llvm::X86Subtarget::hasAVX().

bool X86InstrInfo::shouldScheduleLoadsNear	(	SDNode *	Load1,
		SDNode *	Load2,
		int64_t	Offset1,
		int64_t	Offset2,
		unsigned	NumLoads
	)		const

virtual

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

Definition at line 4866 of file X86InstrInfo.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::X86TargetMachine::getSubtargetImpl(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), and llvm::MVT::SimpleTy.

void X86InstrInfo::storeRegToAddr	(	MachineFunction &	MF,
		unsigned	SrcReg,
		bool	isKill,
		SmallVectorImpl< MachineOperand > &	Addr,
		const TargetRegisterClass *	RC,
		MachineInstr::mmo_iterator	MMOBegin,
		MachineInstr::mmo_iterator	MMOEnd,
		SmallVectorImpl< MachineInstr * > &	NewMIs
	)		const

virtual

Definition at line 3232 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineMemOperand::getAlignment(), llvm::getKillRegState(), llvm::TargetRegisterClass::getSize(), getStoreRegOpcode(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by unfoldMemoryOperand().

void X86InstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

virtual

Definition at line 3215 of file X86InstrInfo.cpp.

References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::X86TargetMachine::getFrameLowering(), llvm::getKillRegState(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), llvm::TargetFrameLowering::getStackAlignment(), and getStoreRegOpcode().

bool X86InstrInfo::unfoldMemoryOperand	(	MachineFunction &	MF,
		MachineInstr *	MI,
		unsigned	Reg,
		bool	UnfoldLoad,
		bool	UnfoldStore,
		SmallVectorImpl< MachineInstr * > &	NewMIs
	)		const

virtual

unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. If this is possible, returns true as well as the new instructions by reference.

Definition at line 4511 of file X86InstrInfo.cpp.

bool X86InstrInfo::unfoldMemoryOperand	(	SelectionDAG &	DAG,
		SDNode *	N,
		SmallVectorImpl< SDNode * > &	NewNodes
	)		const

virtual

Definition at line 4637 of file X86InstrInfo.cpp.

References llvm::X86::AddrNumOperands, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::end(), llvm::MachineFunction::extractLoadMemRefs(), llvm::MachineFunction::extractStoreMemRefs(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::find(), getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOperand(), llvm::TargetRegisterClass::getSize(), getStoreRegOpcode(), llvm::TargetMachine::getSubtarget(), llvm::SDNode::getValueType(), I, llvm::SDNode::isMachineOpcode(), llvm::X86Subtarget::isUnalignedMemAccessFast(), llvm::SPII::Load, llvm::MCInstrDesc::NumDefs, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SPII::Store, TB_FOLDED_LOAD, TB_FOLDED_STORE, TB_INDEX_MASK, and llvm::TargetRegisterClass::vt_begin().

The documentation for this class was generated from the following files:

Public Member Functions

Static Public Member Functions

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation