68 void resetUnwindDirectiveParserState() {
70 CantUnwindLoc =
SMLoc();
71 PersonalityLoc =
SMLoc();
72 HandlerDataLoc =
SMLoc();
79 bool NextSymbolIsThumb;
100 bool inITBlock() {
return ITState.CurPosition != ~0U;}
101 void forwardITPosition() {
102 if (!inITBlock())
return;
106 if (++ITState.CurPosition == 5 - TZ)
107 ITState.CurPosition = ~0U;
112 MCAsmLexer &getLexer()
const {
return Parser.getLexer(); }
116 return Parser.Warning(L, Msg, Ranges);
120 return Parser.Error(L, Msg, Ranges);
123 int tryParseRegister();
131 unsigned &ShiftAmount);
132 bool parseDirectiveWord(
unsigned Size,
SMLoc L);
133 bool parseDirectiveThumb(
SMLoc L);
134 bool parseDirectiveARM(
SMLoc L);
135 bool parseDirectiveThumbFunc(
SMLoc L);
136 bool parseDirectiveCode(
SMLoc L);
137 bool parseDirectiveSyntax(
SMLoc L);
139 bool parseDirectiveUnreq(
SMLoc L);
140 bool parseDirectiveArch(
SMLoc L);
141 bool parseDirectiveEabiAttr(
SMLoc L);
142 bool parseDirectiveCPU(
SMLoc L);
143 bool parseDirectiveFPU(
SMLoc L);
144 bool parseDirectiveFnStart(
SMLoc L);
145 bool parseDirectiveFnEnd(
SMLoc L);
146 bool parseDirectiveCantUnwind(
SMLoc L);
147 bool parseDirectivePersonality(
SMLoc L);
148 bool parseDirectiveHandlerData(
SMLoc L);
149 bool parseDirectiveSetFP(
SMLoc L);
150 bool parseDirectivePad(
SMLoc L);
151 bool parseDirectiveRegSave(
SMLoc L,
bool IsVector);
154 bool &CarrySetting,
unsigned &ProcessorIMod,
157 bool &CanAcceptCarrySet,
158 bool &CanAcceptPredicationCode);
160 bool isThumb()
const {
162 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
164 bool isThumbOne()
const {
165 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
167 bool isThumbTwo()
const {
168 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
170 bool hasThumb()
const {
171 return STI.getFeatureBits() & ARM::HasV4TOps;
173 bool hasV6Ops()
const {
174 return STI.getFeatureBits() & ARM::HasV6Ops;
176 bool hasV6MOps()
const {
177 return STI.getFeatureBits() & ARM::HasV6MOps;
179 bool hasV7Ops()
const {
180 return STI.getFeatureBits() & ARM::HasV7Ops;
182 bool hasV8Ops()
const {
183 return STI.getFeatureBits() & ARM::HasV8Ops;
185 bool hasARM()
const {
186 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
190 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
191 setAvailableFeatures(FB);
193 bool isMClass()
const {
194 return STI.getFeatureBits() & ARM::FeatureMClass;
200 #define GET_ASSEMBLER_HEADER
201 #include "ARMGenAsmMatcher.inc"
206 OperandMatchResultTy parseCoprocNumOperand(
208 OperandMatchResultTy parseCoprocRegOperand(
210 OperandMatchResultTy parseCoprocOptionOperand(
212 OperandMatchResultTy parseMemBarrierOptOperand(
214 OperandMatchResultTy parseInstSyncBarrierOptOperand(
216 OperandMatchResultTy parseProcIFlagsOperand(
218 OperandMatchResultTy parseMSRMaskOperand(
223 return parsePKHImm(O,
"lsl", 0, 31);
226 return parsePKHImm(O,
"asr", 1, 32);
236 OperandMatchResultTy parseVectorLane(
VectorLaneTy &LaneKind,
unsigned &Index,
240 void cvtThumbMultiply(
MCInst &Inst,
242 void cvtThumbBranches(
MCInst &Inst,
245 bool validateInstruction(
MCInst &Inst,
247 bool processInstruction(
MCInst &Inst,
249 bool shouldOmitCCOutOperand(
StringRef Mnemonic,
251 bool shouldOmitPredicateOperand(
StringRef Mnemonic,
254 enum ARMMatchResultTy {
255 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
256 Match_RequiresNotITBlock,
258 Match_RequiresThumb2,
259 #define GET_OPERAND_DIAGNOSTIC_TYPES
260 #include "ARMGenAsmMatcher.inc"
270 MRI = getContext().getRegisterInfo();
273 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
276 ITState.CurPosition = ~0U;
278 NextSymbolIsThumb =
false;
282 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc);
286 bool ParseDirective(
AsmToken DirectiveID);
289 unsigned checkTargetMatchPredicate(
MCInst &Inst);
291 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
294 bool MatchingInlineAsm);
314 k_InstSyncBarrierOpt,
325 k_VectorListAllLanes,
331 k_BitfieldDescriptor,
335 SMLoc StartLoc, EndLoc;
346 struct CoprocOptionOp {
380 struct VectorListOp {
387 struct VectorIndexOp {
401 unsigned OffsetRegNum;
406 unsigned isNegative : 1;
409 struct PostIdxRegOp {
416 struct ShifterImmOp {
421 struct RegShiftedRegOp {
428 struct RegShiftedImmOp {
446 struct CoprocOptionOp CoprocOption;
447 struct MBOptOp MBOpt;
448 struct ISBOptOp ISBOpt;
449 struct ITMaskOp ITMask;
451 struct MMaskOp MMask;
454 struct VectorListOp VectorList;
455 struct VectorIndexOp VectorIndex;
458 struct PostIdxRegOp PostIdxReg;
459 struct ShifterImmOp ShifterImm;
460 struct RegShiftedRegOp RegShiftedReg;
461 struct RegShiftedImmOp RegShiftedImm;
462 struct RotImmOp RotImm;
463 struct BitfieldOp Bitfield;
470 StartLoc = o.StartLoc;
487 case k_DPRRegisterList:
488 case k_SPRRegisterList:
489 Registers = o.Registers;
492 case k_VectorListAllLanes:
493 case k_VectorListIndexed:
494 VectorList = o.VectorList;
501 CoprocOption = o.CoprocOption;
506 case k_MemBarrierOpt:
509 case k_InstSyncBarrierOpt:
514 case k_PostIndexRegister:
515 PostIdxReg = o.PostIdxReg;
523 case k_ShifterImmediate:
524 ShifterImm = o.ShifterImm;
526 case k_ShiftedRegister:
527 RegShiftedReg = o.RegShiftedReg;
529 case k_ShiftedImmediate:
530 RegShiftedImm = o.RegShiftedImm;
532 case k_RotateImmediate:
535 case k_BitfieldDescriptor:
536 Bitfield = o.Bitfield;
539 VectorIndex = o.VectorIndex;
545 SMLoc getStartLoc()
const {
return StartLoc; }
547 SMLoc getEndLoc()
const {
return EndLoc; }
553 assert(
Kind == k_CondCode &&
"Invalid access!");
557 unsigned getCoproc()
const {
558 assert((
Kind == k_CoprocNum ||
Kind == k_CoprocReg) &&
"Invalid access!");
563 assert(
Kind == k_Token &&
"Invalid access!");
568 assert((
Kind == k_Register ||
Kind == k_CCOut) &&
"Invalid access!");
573 assert((
Kind == k_RegisterList ||
Kind == k_DPRRegisterList ||
574 Kind == k_SPRRegisterList) &&
"Invalid access!");
578 const MCExpr *getImm()
const {
579 assert(isImm() &&
"Invalid access!");
583 unsigned getVectorIndex()
const {
584 assert(
Kind == k_VectorIndex &&
"Invalid access!");
585 return VectorIndex.Val;
589 assert(
Kind == k_MemBarrierOpt &&
"Invalid access!");
594 assert(
Kind == k_InstSyncBarrierOpt &&
"Invalid access!");
599 assert(
Kind == k_ProcIFlags &&
"Invalid access!");
603 unsigned getMSRMask()
const {
604 assert(
Kind == k_MSRMask &&
"Invalid access!");
608 bool isCoprocNum()
const {
return Kind == k_CoprocNum; }
609 bool isCoprocReg()
const {
return Kind == k_CoprocReg; }
610 bool isCoprocOption()
const {
return Kind == k_CoprocOption; }
611 bool isCondCode()
const {
return Kind == k_CondCode; }
612 bool isCCOut()
const {
return Kind == k_CCOut; }
613 bool isITMask()
const {
return Kind == k_ITCondMask; }
614 bool isITCondCode()
const {
return Kind == k_CondCode; }
615 bool isImm()
const {
return Kind == k_Immediate; }
618 template<
unsigned w
idth,
unsigned scale>
619 bool isUnsignedOffset()
const {
620 if (!isImm())
return false;
621 if (isa<MCSymbolRefExpr>(Imm.Val))
return true;
622 if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
623 int64_t Val = CE->getValue();
624 int64_t
Align = 1LL << scale;
625 int64_t Max = Align * ((1LL << width) - 1);
626 return ((Val %
Align) == 0) && (Val >= 0) && (Val <= Max);
632 template<
unsigned w
idth,
unsigned scale>
633 bool isSignedOffset()
const {
634 if (!isImm())
return false;
635 if (isa<MCSymbolRefExpr>(Imm.Val))
return true;
636 if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
637 int64_t Val = CE->getValue();
638 int64_t
Align = 1LL << scale;
639 int64_t Max = Align * ((1LL << (width-1)) - 1);
640 int64_t Min = -
Align * (1LL << (width-1));
641 return ((Val %
Align) == 0) && (Val >= Min) && (Val <= Max);
650 bool isThumbMemPC()
const {
653 if (isa<MCSymbolRefExpr>(Imm.Val))
return true;
655 if (!CE)
return false;
659 if(!
Memory.OffsetImm ||
Memory.OffsetRegNum)
return false;
660 if(
Memory.BaseRegNum != ARM::PC)
return false;
661 Val =
Memory.OffsetImm->getValue();
664 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
667 if (!isImm())
return false;
669 if (!CE)
return false;
673 bool isFBits16()
const {
674 if (!isImm())
return false;
676 if (!CE)
return false;
678 return Value >= 0 && Value <= 16;
680 bool isFBits32()
const {
681 if (!isImm())
return false;
683 if (!CE)
return false;
685 return Value >= 1 && Value <= 32;
687 bool isImm8s4()
const {
688 if (!isImm())
return false;
690 if (!CE)
return false;
692 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
694 bool isImm0_1020s4()
const {
695 if (!isImm())
return false;
697 if (!CE)
return false;
699 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
701 bool isImm0_508s4()
const {
702 if (!isImm())
return false;
704 if (!CE)
return false;
706 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
708 bool isImm0_508s4Neg()
const {
709 if (!isImm())
return false;
711 if (!CE)
return false;
714 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
716 bool isImm0_239()
const {
717 if (!isImm())
return false;
719 if (!CE)
return false;
721 return Value >= 0 && Value < 240;
723 bool isImm0_255()
const {
724 if (!isImm())
return false;
726 if (!CE)
return false;
728 return Value >= 0 && Value < 256;
730 bool isImm0_4095()
const {
731 if (!isImm())
return false;
733 if (!CE)
return false;
735 return Value >= 0 && Value < 4096;
737 bool isImm0_4095Neg()
const {
738 if (!isImm())
return false;
740 if (!CE)
return false;
742 return Value > 0 && Value < 4096;
744 bool isImm0_1()
const {
745 if (!isImm())
return false;
747 if (!CE)
return false;
749 return Value >= 0 && Value < 2;
751 bool isImm0_3()
const {
752 if (!isImm())
return false;
754 if (!CE)
return false;
756 return Value >= 0 && Value < 4;
758 bool isImm0_7()
const {
759 if (!isImm())
return false;
761 if (!CE)
return false;
763 return Value >= 0 && Value < 8;
765 bool isImm0_15()
const {
766 if (!isImm())
return false;
768 if (!CE)
return false;
770 return Value >= 0 && Value < 16;
772 bool isImm0_31()
const {
773 if (!isImm())
return false;
775 if (!CE)
return false;
777 return Value >= 0 && Value < 32;
779 bool isImm0_63()
const {
780 if (!isImm())
return false;
782 if (!CE)
return false;
784 return Value >= 0 && Value < 64;
786 bool isImm8()
const {
787 if (!isImm())
return false;
789 if (!CE)
return false;
793 bool isImm16()
const {
794 if (!isImm())
return false;
796 if (!CE)
return false;
800 bool isImm32()
const {
801 if (!isImm())
return false;
803 if (!CE)
return false;
807 bool isShrImm8()
const {
808 if (!isImm())
return false;
810 if (!CE)
return false;
812 return Value > 0 && Value <= 8;
814 bool isShrImm16()
const {
815 if (!isImm())
return false;
817 if (!CE)
return false;
819 return Value > 0 && Value <= 16;
821 bool isShrImm32()
const {
822 if (!isImm())
return false;
824 if (!CE)
return false;
826 return Value > 0 && Value <= 32;
828 bool isShrImm64()
const {
829 if (!isImm())
return false;
831 if (!CE)
return false;
833 return Value > 0 && Value <= 64;
835 bool isImm1_7()
const {
836 if (!isImm())
return false;
838 if (!CE)
return false;
840 return Value > 0 && Value < 8;
842 bool isImm1_15()
const {
843 if (!isImm())
return false;
845 if (!CE)
return false;
847 return Value > 0 && Value < 16;
849 bool isImm1_31()
const {
850 if (!isImm())
return false;
852 if (!CE)
return false;
854 return Value > 0 && Value < 32;
856 bool isImm1_16()
const {
857 if (!isImm())
return false;
859 if (!CE)
return false;
861 return Value > 0 && Value < 17;
863 bool isImm1_32()
const {
864 if (!isImm())
return false;
866 if (!CE)
return false;
868 return Value > 0 && Value < 33;
870 bool isImm0_32()
const {
871 if (!isImm())
return false;
873 if (!CE)
return false;
875 return Value >= 0 && Value < 33;
877 bool isImm0_65535()
const {
878 if (!isImm())
return false;
880 if (!CE)
return false;
882 return Value >= 0 && Value < 65536;
884 bool isImm256_65535Expr()
const {
885 if (!isImm())
return false;
889 if (!CE)
return true;
891 return Value >= 256 && Value < 65536;
893 bool isImm0_65535Expr()
const {
894 if (!isImm())
return false;
898 if (!CE)
return true;
900 return Value >= 0 && Value < 65536;
902 bool isImm24bit()
const {
903 if (!isImm())
return false;
905 if (!CE)
return false;
907 return Value >= 0 && Value <= 0xffffff;
909 bool isImmThumbSR()
const {
910 if (!isImm())
return false;
912 if (!CE)
return false;
914 return Value > 0 && Value < 33;
916 bool isPKHLSLImm()
const {
917 if (!isImm())
return false;
919 if (!CE)
return false;
921 return Value >= 0 && Value < 32;
923 bool isPKHASRImm()
const {
924 if (!isImm())
return false;
926 if (!CE)
return false;
928 return Value > 0 && Value <= 32;
930 bool isAdrLabel()
const {
934 if (isImm() && !isa<MCConstantExpr>(getImm()))
return true;
935 else return (isARMSOImm() || isARMSOImmNeg());
937 bool isARMSOImm()
const {
938 if (!isImm())
return false;
940 if (!CE)
return false;
944 bool isARMSOImmNot()
const {
945 if (!isImm())
return false;
947 if (!CE)
return false;
951 bool isARMSOImmNeg()
const {
952 if (!isImm())
return false;
954 if (!CE)
return false;
960 bool isT2SOImm()
const {
961 if (!isImm())
return false;
963 if (!CE)
return false;
967 bool isT2SOImmNot()
const {
968 if (!isImm())
return false;
970 if (!CE)
return false;
975 bool isT2SOImmNeg()
const {
976 if (!isImm())
return false;
978 if (!CE)
return false;
984 bool isSetEndImm()
const {
985 if (!isImm())
return false;
987 if (!CE)
return false;
989 return Value == 1 || Value == 0;
991 bool isReg()
const {
return Kind == k_Register; }
992 bool isRegList()
const {
return Kind == k_RegisterList; }
993 bool isDPRRegList()
const {
return Kind == k_DPRRegisterList; }
994 bool isSPRRegList()
const {
return Kind == k_SPRRegisterList; }
995 bool isToken()
const {
return Kind == k_Token; }
996 bool isMemBarrierOpt()
const {
return Kind == k_MemBarrierOpt; }
997 bool isInstSyncBarrierOpt()
const {
return Kind == k_InstSyncBarrierOpt; }
998 bool isMem()
const {
return Kind == k_Memory; }
999 bool isShifterImm()
const {
return Kind == k_ShifterImmediate; }
1000 bool isRegShiftedReg()
const {
return Kind == k_ShiftedRegister; }
1001 bool isRegShiftedImm()
const {
return Kind == k_ShiftedImmediate; }
1002 bool isRotImm()
const {
return Kind == k_RotateImmediate; }
1003 bool isBitfield()
const {
return Kind == k_BitfieldDescriptor; }
1004 bool isPostIdxRegShifted()
const {
return Kind == k_PostIndexRegister; }
1005 bool isPostIdxReg()
const {
1008 bool isMemNoOffset(
bool alignOK =
false)
const {
1012 return Memory.OffsetRegNum == 0 &&
Memory.OffsetImm == 0 &&
1013 (alignOK ||
Memory.Alignment == 0);
1015 bool isMemPCRelImm12()
const {
1019 if (
Memory.BaseRegNum != ARM::PC)
1022 if (!
Memory.OffsetImm)
return true;
1023 int64_t Val =
Memory.OffsetImm->getValue();
1024 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1026 bool isAlignedMemory()
const {
1027 return isMemNoOffset(
true);
1029 bool isAddrMode2()
const {
1030 if (!
isMem() ||
Memory.Alignment != 0)
return false;
1032 if (
Memory.OffsetRegNum)
return true;
1034 if (!
Memory.OffsetImm)
return true;
1035 int64_t Val =
Memory.OffsetImm->getValue();
1036 return Val > -4096 && Val < 4096;
1038 bool isAM2OffsetImm()
const {
1039 if (!isImm())
return false;
1042 if (!CE)
return false;
1044 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1046 bool isAddrMode3()
const {
1050 if (isImm() && !isa<MCConstantExpr>(getImm()))
1052 if (!
isMem() ||
Memory.Alignment != 0)
return false;
1056 if (
Memory.OffsetRegNum)
return true;
1058 if (!
Memory.OffsetImm)
return true;
1059 int64_t Val =
Memory.OffsetImm->getValue();
1062 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1064 bool isAM3Offset()
const {
1065 if (
Kind != k_Immediate &&
Kind != k_PostIndexRegister)
1067 if (
Kind == k_PostIndexRegister)
1071 if (!CE)
return false;
1074 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1076 bool isAddrMode5()
const {
1080 if (isImm() && !isa<MCConstantExpr>(getImm()))
1082 if (!
isMem() ||
Memory.Alignment != 0)
return false;
1084 if (
Memory.OffsetRegNum)
return false;
1086 if (!
Memory.OffsetImm)
return true;
1087 int64_t Val =
Memory.OffsetImm->getValue();
1088 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1091 bool isMemTBB()
const {
1097 bool isMemTBH()
const {
1104 bool isMemRegOffset()
const {
1109 bool isT2MemRegOffset()
const {
1120 bool isMemThumbRR()
const {
1129 bool isMemThumbRIs4()
const {
1134 if (!
Memory.OffsetImm)
return true;
1135 int64_t Val =
Memory.OffsetImm->getValue();
1136 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1138 bool isMemThumbRIs2()
const {
1143 if (!
Memory.OffsetImm)
return true;
1144 int64_t Val =
Memory.OffsetImm->getValue();
1145 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1147 bool isMemThumbRIs1()
const {
1152 if (!
Memory.OffsetImm)
return true;
1153 int64_t Val =
Memory.OffsetImm->getValue();
1154 return Val >= 0 && Val <= 31;
1156 bool isMemThumbSPI()
const {
1161 if (!
Memory.OffsetImm)
return true;
1162 int64_t Val =
Memory.OffsetImm->getValue();
1163 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1165 bool isMemImm8s4Offset()
const {
1169 if (isImm() && !isa<MCConstantExpr>(getImm()))
1174 if (!
Memory.OffsetImm)
return true;
1175 int64_t Val =
Memory.OffsetImm->getValue();
1177 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1179 bool isMemImm0_1020s4Offset()
const {
1183 if (!
Memory.OffsetImm)
return true;
1184 int64_t Val =
Memory.OffsetImm->getValue();
1185 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1187 bool isMemImm8Offset()
const {
1191 if (
Memory.BaseRegNum == ARM::PC)
return false;
1193 if (!
Memory.OffsetImm)
return true;
1194 int64_t Val =
Memory.OffsetImm->getValue();
1195 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1197 bool isMemPosImm8Offset()
const {
1201 if (!
Memory.OffsetImm)
return true;
1202 int64_t Val =
Memory.OffsetImm->getValue();
1203 return Val >= 0 && Val < 256;
1205 bool isMemNegImm8Offset()
const {
1209 if (
Memory.BaseRegNum == ARM::PC)
return false;
1211 if (!
Memory.OffsetImm)
return false;
1212 int64_t Val =
Memory.OffsetImm->getValue();
1213 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1215 bool isMemUImm12Offset()
const {
1219 if (!
Memory.OffsetImm)
return true;
1220 int64_t Val =
Memory.OffsetImm->getValue();
1221 return (Val >= 0 && Val < 4096);
1223 bool isMemImm12Offset()
const {
1227 if (isImm() && !isa<MCConstantExpr>(getImm()))
1233 if (!
Memory.OffsetImm)
return true;
1234 int64_t Val =
Memory.OffsetImm->getValue();
1235 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1237 bool isPostIdxImm8()
const {
1238 if (!isImm())
return false;
1240 if (!CE)
return false;
1242 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1244 bool isPostIdxImm8s4()
const {
1245 if (!isImm())
return false;
1247 if (!CE)
return false;
1249 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1253 bool isMSRMask()
const {
return Kind == k_MSRMask; }
1254 bool isProcIFlags()
const {
return Kind == k_ProcIFlags; }
1257 bool isSingleSpacedVectorList()
const {
1258 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1260 bool isDoubleSpacedVectorList()
const {
1261 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1263 bool isVecListOneD()
const {
1264 if (!isSingleSpacedVectorList())
return false;
1265 return VectorList.Count == 1;
1268 bool isVecListDPair()
const {
1269 if (!isSingleSpacedVectorList())
return false;
1270 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1271 .contains(VectorList.RegNum));
1274 bool isVecListThreeD()
const {
1275 if (!isSingleSpacedVectorList())
return false;
1276 return VectorList.Count == 3;
1279 bool isVecListFourD()
const {
1280 if (!isSingleSpacedVectorList())
return false;
1281 return VectorList.Count == 4;
1284 bool isVecListDPairSpaced()
const {
1285 if (isSingleSpacedVectorList())
return false;
1286 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1287 .contains(VectorList.RegNum));
1290 bool isVecListThreeQ()
const {
1291 if (!isDoubleSpacedVectorList())
return false;
1292 return VectorList.Count == 3;
1295 bool isVecListFourQ()
const {
1296 if (!isDoubleSpacedVectorList())
return false;
1297 return VectorList.Count == 4;
1300 bool isSingleSpacedVectorAllLanes()
const {
1301 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1303 bool isDoubleSpacedVectorAllLanes()
const {
1304 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1306 bool isVecListOneDAllLanes()
const {
1307 if (!isSingleSpacedVectorAllLanes())
return false;
1308 return VectorList.Count == 1;
1311 bool isVecListDPairAllLanes()
const {
1312 if (!isSingleSpacedVectorAllLanes())
return false;
1313 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1314 .contains(VectorList.RegNum));
1317 bool isVecListDPairSpacedAllLanes()
const {
1318 if (!isDoubleSpacedVectorAllLanes())
return false;
1319 return VectorList.Count == 2;
1322 bool isVecListThreeDAllLanes()
const {
1323 if (!isSingleSpacedVectorAllLanes())
return false;
1324 return VectorList.Count == 3;
1327 bool isVecListThreeQAllLanes()
const {
1328 if (!isDoubleSpacedVectorAllLanes())
return false;
1329 return VectorList.Count == 3;
1332 bool isVecListFourDAllLanes()
const {
1333 if (!isSingleSpacedVectorAllLanes())
return false;
1334 return VectorList.Count == 4;
1337 bool isVecListFourQAllLanes()
const {
1338 if (!isDoubleSpacedVectorAllLanes())
return false;
1339 return VectorList.Count == 4;
1342 bool isSingleSpacedVectorIndexed()
const {
1343 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1345 bool isDoubleSpacedVectorIndexed()
const {
1346 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1348 bool isVecListOneDByteIndexed()
const {
1349 if (!isSingleSpacedVectorIndexed())
return false;
1350 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1353 bool isVecListOneDHWordIndexed()
const {
1354 if (!isSingleSpacedVectorIndexed())
return false;
1355 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1358 bool isVecListOneDWordIndexed()
const {
1359 if (!isSingleSpacedVectorIndexed())
return false;
1360 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1363 bool isVecListTwoDByteIndexed()
const {
1364 if (!isSingleSpacedVectorIndexed())
return false;
1365 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1368 bool isVecListTwoDHWordIndexed()
const {
1369 if (!isSingleSpacedVectorIndexed())
return false;
1370 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1373 bool isVecListTwoQWordIndexed()
const {
1374 if (!isDoubleSpacedVectorIndexed())
return false;
1375 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1378 bool isVecListTwoQHWordIndexed()
const {
1379 if (!isDoubleSpacedVectorIndexed())
return false;
1380 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1383 bool isVecListTwoDWordIndexed()
const {
1384 if (!isSingleSpacedVectorIndexed())
return false;
1385 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1388 bool isVecListThreeDByteIndexed()
const {
1389 if (!isSingleSpacedVectorIndexed())
return false;
1390 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1393 bool isVecListThreeDHWordIndexed()
const {
1394 if (!isSingleSpacedVectorIndexed())
return false;
1395 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1398 bool isVecListThreeQWordIndexed()
const {
1399 if (!isDoubleSpacedVectorIndexed())
return false;
1400 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1403 bool isVecListThreeQHWordIndexed()
const {
1404 if (!isDoubleSpacedVectorIndexed())
return false;
1405 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1408 bool isVecListThreeDWordIndexed()
const {
1409 if (!isSingleSpacedVectorIndexed())
return false;
1410 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1413 bool isVecListFourDByteIndexed()
const {
1414 if (!isSingleSpacedVectorIndexed())
return false;
1415 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1418 bool isVecListFourDHWordIndexed()
const {
1419 if (!isSingleSpacedVectorIndexed())
return false;
1420 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1423 bool isVecListFourQWordIndexed()
const {
1424 if (!isDoubleSpacedVectorIndexed())
return false;
1425 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1428 bool isVecListFourQHWordIndexed()
const {
1429 if (!isDoubleSpacedVectorIndexed())
return false;
1430 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1433 bool isVecListFourDWordIndexed()
const {
1434 if (!isSingleSpacedVectorIndexed())
return false;
1435 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1438 bool isVectorIndex8()
const {
1439 if (
Kind != k_VectorIndex)
return false;
1440 return VectorIndex.Val < 8;
1442 bool isVectorIndex16()
const {
1443 if (
Kind != k_VectorIndex)
return false;
1444 return VectorIndex.Val < 4;
1446 bool isVectorIndex32()
const {
1447 if (
Kind != k_VectorIndex)
return false;
1448 return VectorIndex.Val < 2;
1451 bool isNEONi8splat()
const {
1452 if (!isImm())
return false;
1455 if (!CE)
return false;
1459 return Value >= 0 && Value < 256;
1462 bool isNEONi16splat()
const {
1463 if (!isImm())
return false;
1466 if (!CE)
return false;
1469 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1472 bool isNEONi32splat()
const {
1473 if (!isImm())
return false;
1476 if (!CE)
return false;
1479 return (Value >= 0 && Value < 256) ||
1480 (Value >= 0x0100 && Value <= 0xff00) ||
1481 (Value >= 0x010000 && Value <= 0xff0000) ||
1482 (Value >= 0x01000000 && Value <= 0xff000000);
1485 bool isNEONi32vmov()
const {
1486 if (!isImm())
return false;
1489 if (!CE)
return false;
1493 return (Value >= 0 && Value < 256) ||
1494 (Value >= 0x0100 && Value <= 0xff00) ||
1495 (Value >= 0x010000 && Value <= 0xff0000) ||
1496 (Value >= 0x01000000 && Value <= 0xff000000) ||
1497 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1498 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1500 bool isNEONi32vmovNeg()
const {
1501 if (!isImm())
return false;
1504 if (!CE)
return false;
1508 return (Value >= 0 && Value < 256) ||
1509 (Value >= 0x0100 && Value <= 0xff00) ||
1510 (Value >= 0x010000 && Value <= 0xff0000) ||
1511 (Value >= 0x01000000 && Value <= 0xff000000) ||
1512 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1513 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1516 bool isNEONi64splat()
const {
1517 if (!isImm())
return false;
1520 if (!CE)
return false;
1523 for (
unsigned i = 0; i < 8; ++i)
1524 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff)
return false;
1532 else if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1538 void addCondCodeOperands(
MCInst &Inst,
unsigned N)
const {
1539 assert(N == 2 &&
"Invalid number of operands!");
1541 unsigned RegNum = getCondCode() ==
ARMCC::AL ? 0: ARM::CPSR;
1545 void addCoprocNumOperands(
MCInst &Inst,
unsigned N)
const {
1546 assert(N == 1 &&
"Invalid number of operands!");
1550 void addCoprocRegOperands(
MCInst &Inst,
unsigned N)
const {
1551 assert(N == 1 &&
"Invalid number of operands!");
1555 void addCoprocOptionOperands(
MCInst &Inst,
unsigned N)
const {
1556 assert(N == 1 &&
"Invalid number of operands!");
1560 void addITMaskOperands(
MCInst &Inst,
unsigned N)
const {
1561 assert(N == 1 &&
"Invalid number of operands!");
1565 void addITCondCodeOperands(
MCInst &Inst,
unsigned N)
const {
1566 assert(N == 1 &&
"Invalid number of operands!");
1570 void addCCOutOperands(
MCInst &Inst,
unsigned N)
const {
1571 assert(N == 1 &&
"Invalid number of operands!");
1575 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
1576 assert(N == 1 &&
"Invalid number of operands!");
1580 void addRegShiftedRegOperands(
MCInst &Inst,
unsigned N)
const {
1581 assert(N == 3 &&
"Invalid number of operands!");
1582 assert(isRegShiftedReg() &&
1583 "addRegShiftedRegOperands() on non RegShiftedReg!");
1590 void addRegShiftedImmOperands(
MCInst &Inst,
unsigned N)
const {
1591 assert(N == 2 &&
"Invalid number of operands!");
1592 assert(isRegShiftedImm() &&
1593 "addRegShiftedImmOperands() on non RegShiftedImm!");
1596 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1601 void addShifterImmOperands(
MCInst &Inst,
unsigned N)
const {
1602 assert(N == 1 &&
"Invalid number of operands!");
1607 void addRegListOperands(
MCInst &Inst,
unsigned N)
const {
1608 assert(N == 1 &&
"Invalid number of operands!");
1611 I = RegList.
begin(), E = RegList.
end();
I != E; ++
I)
1615 void addDPRRegListOperands(
MCInst &Inst,
unsigned N)
const {
1616 addRegListOperands(Inst, N);
1619 void addSPRRegListOperands(
MCInst &Inst,
unsigned N)
const {
1620 addRegListOperands(Inst, N);
1623 void addRotImmOperands(
MCInst &Inst,
unsigned N)
const {
1624 assert(N == 1 &&
"Invalid number of operands!");
1629 void addBitfieldOperands(
MCInst &Inst,
unsigned N)
const {
1630 assert(N == 1 &&
"Invalid number of operands!");
1632 unsigned lsb = Bitfield.LSB;
1633 unsigned width = Bitfield.Width;
1635 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1636 (32 - (lsb + width)));
1640 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
1641 assert(N == 1 &&
"Invalid number of operands!");
1642 addExpr(Inst, getImm());
1645 void addFBits16Operands(
MCInst &Inst,
unsigned N)
const {
1646 assert(N == 1 &&
"Invalid number of operands!");
1651 void addFBits32Operands(
MCInst &Inst,
unsigned N)
const {
1652 assert(N == 1 &&
"Invalid number of operands!");
1657 void addFPImmOperands(
MCInst &Inst,
unsigned N)
const {
1658 assert(N == 1 &&
"Invalid number of operands!");
1664 void addImm8s4Operands(
MCInst &Inst,
unsigned N)
const {
1665 assert(N == 1 &&
"Invalid number of operands!");
1672 void addImm0_1020s4Operands(
MCInst &Inst,
unsigned N)
const {
1673 assert(N == 1 &&
"Invalid number of operands!");
1680 void addImm0_508s4NegOperands(
MCInst &Inst,
unsigned N)
const {
1681 assert(N == 1 &&
"Invalid number of operands!");
1688 void addImm0_508s4Operands(
MCInst &Inst,
unsigned N)
const {
1689 assert(N == 1 &&
"Invalid number of operands!");
1696 void addImm1_16Operands(
MCInst &Inst,
unsigned N)
const {
1697 assert(N == 1 &&
"Invalid number of operands!");
1704 void addImm1_32Operands(
MCInst &Inst,
unsigned N)
const {
1705 assert(N == 1 &&
"Invalid number of operands!");
1712 void addImmThumbSROperands(
MCInst &Inst,
unsigned N)
const {
1713 assert(N == 1 &&
"Invalid number of operands!");
1721 void addPKHASRImmOperands(
MCInst &Inst,
unsigned N)
const {
1722 assert(N == 1 &&
"Invalid number of operands!");
1730 void addT2SOImmNotOperands(
MCInst &Inst,
unsigned N)
const {
1731 assert(N == 1 &&
"Invalid number of operands!");
1738 void addT2SOImmNegOperands(
MCInst &Inst,
unsigned N)
const {
1739 assert(N == 1 &&
"Invalid number of operands!");
1746 void addImm0_4095NegOperands(
MCInst &Inst,
unsigned N)
const {
1747 assert(N == 1 &&
"Invalid number of operands!");
1754 void addUnsignedOffset_b8s2Operands(
MCInst &Inst,
unsigned N)
const {
1755 if(
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1761 assert(SR &&
"Unknown value type!");
1765 void addThumbMemPCOperands(
MCInst &Inst,
unsigned N)
const {
1766 assert(N == 1 &&
"Invalid number of operands!");
1775 assert(SR &&
"Unknown value type!");
1780 assert(
isMem() &&
"Unknown value type!");
1781 assert(isa<MCConstantExpr>(
Memory.OffsetImm) &&
"Unknown value type!");
1785 void addARMSOImmNotOperands(
MCInst &Inst,
unsigned N)
const {
1786 assert(N == 1 &&
"Invalid number of operands!");
1793 void addARMSOImmNegOperands(
MCInst &Inst,
unsigned N)
const {
1794 assert(N == 1 &&
"Invalid number of operands!");
1801 void addMemBarrierOptOperands(
MCInst &Inst,
unsigned N)
const {
1802 assert(N == 1 &&
"Invalid number of operands!");
1806 void addInstSyncBarrierOptOperands(
MCInst &Inst,
unsigned N)
const {
1807 assert(N == 1 &&
"Invalid number of operands!");
1811 void addMemNoOffsetOperands(
MCInst &Inst,
unsigned N)
const {
1812 assert(N == 1 &&
"Invalid number of operands!");
1816 void addMemPCRelImm12Operands(
MCInst &Inst,
unsigned N)
const {
1817 assert(N == 1 &&
"Invalid number of operands!");
1818 int32_t Imm =
Memory.OffsetImm->getValue();
1822 void addAdrLabelOperands(
MCInst &Inst,
unsigned N)
const {
1823 assert(N == 1 &&
"Invalid number of operands!");
1824 assert(isImm() &&
"Not an immediate!");
1828 if (!isa<MCConstantExpr>(getImm())) {
1838 void addAlignedMemoryOperands(
MCInst &Inst,
unsigned N)
const {
1839 assert(N == 2 &&
"Invalid number of operands!");
1844 void addAddrMode2Operands(
MCInst &Inst,
unsigned N)
const {
1845 assert(N == 3 &&
"Invalid number of operands!");
1846 int32_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() : 0;
1847 if (!
Memory.OffsetRegNum) {
1850 if (Val == INT32_MIN) Val = 0;
1851 if (Val < 0) Val = -Val;
1864 void addAM2OffsetImmOperands(
MCInst &Inst,
unsigned N)
const {
1865 assert(N == 2 &&
"Invalid number of operands!");
1867 assert(CE &&
"non-constant AM2OffsetImm operand!");
1871 if (Val == INT32_MIN) Val = 0;
1872 if (Val < 0) Val = -Val;
1878 void addAddrMode3Operands(
MCInst &Inst,
unsigned N)
const {
1879 assert(N == 3 &&
"Invalid number of operands!");
1890 int32_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() : 0;
1891 if (!
Memory.OffsetRegNum) {
1894 if (Val == INT32_MIN) Val = 0;
1895 if (Val < 0) Val = -Val;
1907 void addAM3OffsetOperands(
MCInst &Inst,
unsigned N)
const {
1908 assert(N == 2 &&
"Invalid number of operands!");
1909 if (
Kind == k_PostIndexRegister) {
1922 if (Val == INT32_MIN) Val = 0;
1923 if (Val < 0) Val = -Val;
1929 void addAddrMode5Operands(
MCInst &Inst,
unsigned N)
const {
1930 assert(N == 2 &&
"Invalid number of operands!");
1941 int32_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() / 4 : 0;
1944 if (Val == INT32_MIN) Val = 0;
1945 if (Val < 0) Val = -Val;
1951 void addMemImm8s4OffsetOperands(
MCInst &Inst,
unsigned N)
const {
1952 assert(N == 2 &&
"Invalid number of operands!");
1962 int64_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() : 0;
1967 void addMemImm0_1020s4OffsetOperands(
MCInst &Inst,
unsigned N)
const {
1968 assert(N == 2 &&
"Invalid number of operands!");
1970 int32_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() / 4 : 0;
1975 void addMemImm8OffsetOperands(
MCInst &Inst,
unsigned N)
const {
1976 assert(N == 2 &&
"Invalid number of operands!");
1977 int64_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() : 0;
1982 void addMemPosImm8OffsetOperands(
MCInst &Inst,
unsigned N)
const {
1983 addMemImm8OffsetOperands(Inst, N);
1986 void addMemNegImm8OffsetOperands(
MCInst &Inst,
unsigned N)
const {
1987 addMemImm8OffsetOperands(Inst, N);
1990 void addMemUImm12OffsetOperands(
MCInst &Inst,
unsigned N)
const {
1991 assert(N == 2 &&
"Invalid number of operands!");
1994 addExpr(Inst, getImm());
2000 int64_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() : 0;
2005 void addMemImm12OffsetOperands(
MCInst &Inst,
unsigned N)
const {
2006 assert(N == 2 &&
"Invalid number of operands!");
2009 addExpr(Inst, getImm());
2015 int64_t Val =
Memory.OffsetImm ?
Memory.OffsetImm->getValue() : 0;
2020 void addMemTBBOperands(
MCInst &Inst,
unsigned N)
const {
2021 assert(N == 2 &&
"Invalid number of operands!");
2026 void addMemTBHOperands(
MCInst &Inst,
unsigned N)
const {
2027 assert(N == 2 &&
"Invalid number of operands!");
2032 void addMemRegOffsetOperands(
MCInst &Inst,
unsigned N)
const {
2033 assert(N == 3 &&
"Invalid number of operands!");
2042 void addT2MemRegOffsetOperands(
MCInst &Inst,
unsigned N)
const {
2043 assert(N == 3 &&
"Invalid number of operands!");
2049 void addMemThumbRROperands(
MCInst &Inst,
unsigned N)
const {
2050 assert(N == 2 &&
"Invalid number of operands!");
2055 void addMemThumbRIs4Operands(
MCInst &Inst,
unsigned N)
const {
2056 assert(N == 2 &&
"Invalid number of operands!");
2057 int64_t Val =
Memory.OffsetImm ? (
Memory.OffsetImm->getValue() / 4) : 0;
2062 void addMemThumbRIs2Operands(
MCInst &Inst,
unsigned N)
const {
2063 assert(N == 2 &&
"Invalid number of operands!");
2064 int64_t Val =
Memory.OffsetImm ? (
Memory.OffsetImm->getValue() / 2) : 0;
2069 void addMemThumbRIs1Operands(
MCInst &Inst,
unsigned N)
const {
2070 assert(N == 2 &&
"Invalid number of operands!");
2071 int64_t Val =
Memory.OffsetImm ? (
Memory.OffsetImm->getValue()) : 0;
2076 void addMemThumbSPIOperands(
MCInst &Inst,
unsigned N)
const {
2077 assert(N == 2 &&
"Invalid number of operands!");
2078 int64_t Val =
Memory.OffsetImm ? (
Memory.OffsetImm->getValue() / 4) : 0;
2083 void addPostIdxImm8Operands(
MCInst &Inst,
unsigned N)
const {
2084 assert(N == 1 &&
"Invalid number of operands!");
2086 assert(CE &&
"non-constant post-idx-imm8 operand!");
2088 bool isAdd = Imm >= 0;
2089 if (Imm == INT32_MIN) Imm = 0;
2090 Imm = (Imm < 0 ? -Imm : Imm) | (
int)isAdd << 8;
2094 void addPostIdxImm8s4Operands(
MCInst &Inst,
unsigned N)
const {
2095 assert(N == 1 &&
"Invalid number of operands!");
2097 assert(CE &&
"non-constant post-idx-imm8s4 operand!");
2099 bool isAdd = Imm >= 0;
2100 if (Imm == INT32_MIN) Imm = 0;
2102 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2106 void addPostIdxRegOperands(
MCInst &Inst,
unsigned N)
const {
2107 assert(N == 2 &&
"Invalid number of operands!");
2112 void addPostIdxRegShiftedOperands(
MCInst &Inst,
unsigned N)
const {
2113 assert(N == 2 &&
"Invalid number of operands!");
2119 PostIdxReg.ShiftTy);
2123 void addMSRMaskOperands(
MCInst &Inst,
unsigned N)
const {
2124 assert(N == 1 &&
"Invalid number of operands!");
2128 void addProcIFlagsOperands(
MCInst &Inst,
unsigned N)
const {
2129 assert(N == 1 &&
"Invalid number of operands!");
2133 void addVecListOperands(
MCInst &Inst,
unsigned N)
const {
2134 assert(N == 1 &&
"Invalid number of operands!");
2138 void addVecListIndexedOperands(
MCInst &Inst,
unsigned N)
const {
2139 assert(N == 2 &&
"Invalid number of operands!");
2144 void addVectorIndex8Operands(
MCInst &Inst,
unsigned N)
const {
2145 assert(N == 1 &&
"Invalid number of operands!");
2149 void addVectorIndex16Operands(
MCInst &Inst,
unsigned N)
const {
2150 assert(N == 1 &&
"Invalid number of operands!");
2154 void addVectorIndex32Operands(
MCInst &Inst,
unsigned N)
const {
2155 assert(N == 1 &&
"Invalid number of operands!");
2159 void addNEONi8splatOperands(
MCInst &Inst,
unsigned N)
const {
2160 assert(N == 1 &&
"Invalid number of operands!");
2167 void addNEONi16splatOperands(
MCInst &Inst,
unsigned N)
const {
2168 assert(N == 1 &&
"Invalid number of operands!");
2173 Value = (Value >> 8) | 0xa00;
2179 void addNEONi32splatOperands(
MCInst &Inst,
unsigned N)
const {
2180 assert(N == 1 &&
"Invalid number of operands!");
2184 if (Value >= 256 && Value <= 0xff00)
2185 Value = (Value >> 8) | 0x200;
2186 else if (Value > 0xffff && Value <= 0xff0000)
2187 Value = (Value >> 16) | 0x400;
2188 else if (Value > 0xffffff)
2189 Value = (Value >> 24) | 0x600;
2193 void addNEONi32vmovOperands(
MCInst &Inst,
unsigned N)
const {
2194 assert(N == 1 &&
"Invalid number of operands!");
2198 if (Value >= 256 && Value <= 0xffff)
2199 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2200 else if (Value > 0xffff && Value <= 0xffffff)
2201 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2202 else if (Value > 0xffffff)
2203 Value = (Value >> 24) | 0x600;
2207 void addNEONi32vmovNegOperands(
MCInst &Inst,
unsigned N)
const {
2208 assert(N == 1 &&
"Invalid number of operands!");
2212 if (Value >= 256 && Value <= 0xffff)
2213 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2214 else if (Value > 0xffff && Value <= 0xffffff)
2215 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2216 else if (Value > 0xffffff)
2217 Value = (Value >> 24) | 0x600;
2221 void addNEONi64splatOperands(
MCInst &Inst,
unsigned N)
const {
2222 assert(N == 1 &&
"Invalid number of operands!");
2227 for (
unsigned i = 0; i < 8; ++i, Value >>= 8) {
2228 Imm |= (Value & 1) << i;
2235 static ARMOperand *CreateITMask(
unsigned Mask,
SMLoc S) {
2236 ARMOperand *Op =
new ARMOperand(k_ITCondMask);
2237 Op->ITMask.Mask = Mask;
2244 ARMOperand *Op =
new ARMOperand(k_CondCode);
2251 static ARMOperand *CreateCoprocNum(
unsigned CopVal,
SMLoc S) {
2252 ARMOperand *Op =
new ARMOperand(k_CoprocNum);
2253 Op->Cop.Val = CopVal;
2259 static ARMOperand *CreateCoprocReg(
unsigned CopVal,
SMLoc S) {
2260 ARMOperand *Op =
new ARMOperand(k_CoprocReg);
2261 Op->Cop.Val = CopVal;
2267 static ARMOperand *CreateCoprocOption(
unsigned Val,
SMLoc S,
SMLoc E) {
2268 ARMOperand *Op =
new ARMOperand(k_CoprocOption);
2275 static ARMOperand *CreateCCOut(
unsigned RegNum,
SMLoc S) {
2276 ARMOperand *Op =
new ARMOperand(k_CCOut);
2277 Op->Reg.RegNum = RegNum;
2284 ARMOperand *Op =
new ARMOperand(k_Token);
2285 Op->Tok.Data = Str.
data();
2286 Op->Tok.Length = Str.
size();
2292 static ARMOperand *CreateReg(
unsigned RegNum,
SMLoc S,
SMLoc E) {
2293 ARMOperand *Op =
new ARMOperand(k_Register);
2294 Op->Reg.RegNum = RegNum;
2305 ARMOperand *Op =
new ARMOperand(k_ShiftedRegister);
2306 Op->RegShiftedReg.ShiftTy = ShTy;
2307 Op->RegShiftedReg.SrcReg = SrcReg;
2308 Op->RegShiftedReg.ShiftReg = ShiftReg;
2309 Op->RegShiftedReg.ShiftImm = ShiftImm;
2319 ARMOperand *Op =
new ARMOperand(k_ShiftedImmediate);
2320 Op->RegShiftedImm.ShiftTy = ShTy;
2321 Op->RegShiftedImm.SrcReg = SrcReg;
2322 Op->RegShiftedImm.ShiftImm = ShiftImm;
2328 static ARMOperand *CreateShifterImm(
bool isASR,
unsigned Imm,
2330 ARMOperand *Op =
new ARMOperand(k_ShifterImmediate);
2331 Op->ShifterImm.isASR = isASR;
2332 Op->ShifterImm.Imm = Imm;
2338 static ARMOperand *CreateRotImm(
unsigned Imm,
SMLoc S,
SMLoc E) {
2339 ARMOperand *Op =
new ARMOperand(k_RotateImmediate);
2340 Op->RotImm.Imm = Imm;
2346 static ARMOperand *CreateBitfield(
unsigned LSB,
unsigned Width,
2348 ARMOperand *Op =
new ARMOperand(k_BitfieldDescriptor);
2349 Op->Bitfield.LSB = LSB;
2350 Op->Bitfield.Width = Width;
2359 assert (Regs.size() > 0 &&
"RegList contains no registers?");
2360 KindTy
Kind = k_RegisterList;
2362 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2363 Kind = k_DPRRegisterList;
2364 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2365 contains(Regs.front().second))
2366 Kind = k_SPRRegisterList;
2371 ARMOperand *Op =
new ARMOperand(Kind);
2373 I = Regs.begin(), E = Regs.end();
I != E; ++
I)
2374 Op->Registers.push_back(
I->second);
2375 Op->StartLoc = StartLoc;
2376 Op->EndLoc = EndLoc;
2380 static ARMOperand *CreateVectorList(
unsigned RegNum,
unsigned Count,
2382 ARMOperand *Op =
new ARMOperand(k_VectorList);
2383 Op->VectorList.RegNum = RegNum;
2384 Op->VectorList.Count = Count;
2385 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2391 static ARMOperand *CreateVectorListAllLanes(
unsigned RegNum,
unsigned Count,
2392 bool isDoubleSpaced,
2394 ARMOperand *Op =
new ARMOperand(k_VectorListAllLanes);
2395 Op->VectorList.RegNum = RegNum;
2396 Op->VectorList.Count = Count;
2397 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2403 static ARMOperand *CreateVectorListIndexed(
unsigned RegNum,
unsigned Count,
2405 bool isDoubleSpaced,
2407 ARMOperand *Op =
new ARMOperand(k_VectorListIndexed);
2408 Op->VectorList.RegNum = RegNum;
2409 Op->VectorList.Count = Count;
2410 Op->VectorList.LaneIndex = Index;
2411 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2417 static ARMOperand *CreateVectorIndex(
unsigned Idx,
SMLoc S,
SMLoc E,
2419 ARMOperand *Op =
new ARMOperand(k_VectorIndex);
2420 Op->VectorIndex.Val = Idx;
2427 ARMOperand *Op =
new ARMOperand(k_Immediate);
2434 static ARMOperand *CreateMem(
unsigned BaseRegNum,
2436 unsigned OffsetRegNum,
2442 ARMOperand *Op =
new ARMOperand(k_Memory);
2443 Op->Memory.BaseRegNum = BaseRegNum;
2444 Op->Memory.OffsetImm = OffsetImm;
2445 Op->Memory.OffsetRegNum = OffsetRegNum;
2446 Op->Memory.ShiftType = ShiftType;
2447 Op->Memory.ShiftImm = ShiftImm;
2448 Op->Memory.Alignment = Alignment;
2449 Op->Memory.isNegative = isNegative;
2455 static ARMOperand *CreatePostIdxReg(
unsigned RegNum,
bool isAdd,
2459 ARMOperand *Op =
new ARMOperand(k_PostIndexRegister);
2460 Op->PostIdxReg.RegNum = RegNum;
2461 Op->PostIdxReg.isAdd = isAdd;
2462 Op->PostIdxReg.ShiftTy = ShiftTy;
2463 Op->PostIdxReg.ShiftImm = ShiftImm;
2470 ARMOperand *Op =
new ARMOperand(k_MemBarrierOpt);
2471 Op->MBOpt.Val = Opt;
2479 ARMOperand *Op =
new ARMOperand(k_InstSyncBarrierOpt);
2480 Op->ISBOpt.Val = Opt;
2487 ARMOperand *Op =
new ARMOperand(k_ProcIFlags);
2494 static ARMOperand *CreateMSRMask(
unsigned MMask,
SMLoc S) {
2495 ARMOperand *Op =
new ARMOperand(k_MSRMask);
2496 Op->MMask.Val = MMask;
2511 OS <<
"<ccout " <<
getReg() <<
">";
2513 case k_ITCondMask: {
2514 static const char *
const MaskStr[] = {
2515 "()",
"(t)",
"(e)",
"(tt)",
"(et)",
"(te)",
"(ee)",
"(ttt)",
"(ett)",
2516 "(tet)",
"(eet)",
"(tte)",
"(ete)",
"(tee)",
"(eee)"
2518 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2519 OS <<
"<it-mask " << MaskStr[ITMask.Mask] <<
">";
2523 OS <<
"<coprocessor number: " << getCoproc() <<
">";
2526 OS <<
"<coprocessor register: " << getCoproc() <<
">";
2528 case k_CoprocOption:
2529 OS <<
"<coprocessor option: " << CoprocOption.Val <<
">";
2532 OS <<
"<mask: " << getMSRMask() <<
">";
2535 getImm()->print(OS);
2537 case k_MemBarrierOpt:
2538 OS <<
"<ARM_MB::" <<
MemBOptToString(getMemBarrierOpt(),
false) <<
">";
2540 case k_InstSyncBarrierOpt:
2545 <<
" base:" <<
Memory.BaseRegNum;
2548 case k_PostIndexRegister:
2549 OS <<
"post-idx register " << (PostIdxReg.isAdd ?
"" :
"-")
2550 << PostIdxReg.RegNum;
2553 << PostIdxReg.ShiftImm;
2556 case k_ProcIFlags: {
2557 OS <<
"<ARM_PROC::";
2558 unsigned IFlags = getProcIFlags();
2559 for (
int i=2; i >= 0; --i)
2560 if (IFlags & (1 << i))
2566 OS <<
"<register " <<
getReg() <<
">";
2568 case k_ShifterImmediate:
2569 OS <<
"<shift " << (ShifterImm.isASR ?
"asr" :
"lsl")
2570 <<
" #" << ShifterImm.Imm <<
">";
2572 case k_ShiftedRegister:
2573 OS <<
"<so_reg_reg "
2574 << RegShiftedReg.SrcReg <<
" "
2576 <<
" " << RegShiftedReg.ShiftReg <<
">";
2578 case k_ShiftedImmediate:
2579 OS <<
"<so_reg_imm "
2580 << RegShiftedImm.SrcReg <<
" "
2582 <<
" #" << RegShiftedImm.ShiftImm <<
">";
2584 case k_RotateImmediate:
2585 OS <<
"<ror " <<
" #" << (RotImm.Imm * 8) <<
">";
2587 case k_BitfieldDescriptor:
2588 OS <<
"<bitfield " <<
"lsb: " << Bitfield.LSB
2589 <<
", width: " << Bitfield.Width <<
">";
2591 case k_RegisterList:
2592 case k_DPRRegisterList:
2593 case k_SPRRegisterList: {
2594 OS <<
"<register_list ";
2598 I = RegList.
begin(), E = RegList.
end();
I != E; ) {
2600 if (++I < E) OS <<
", ";
2607 OS <<
"<vector_list " << VectorList.Count <<
" * "
2608 << VectorList.RegNum <<
">";
2610 case k_VectorListAllLanes:
2611 OS <<
"<vector_list(all lanes) " << VectorList.Count <<
" * "
2612 << VectorList.RegNum <<
">";
2614 case k_VectorListIndexed:
2615 OS <<
"<vector_list(lane " << VectorList.LaneIndex <<
") "
2616 << VectorList.Count <<
" * " << VectorList.RegNum <<
">";
2622 OS <<
"<vectorindex " << getVectorIndex() <<
">";
2634 bool ARMAsmParser::ParseRegister(
unsigned &RegNo,
2636 StartLoc = Parser.getTok().getLoc();
2637 EndLoc = Parser.getTok().getEndLoc();
2638 RegNo = tryParseRegister();
2640 return (RegNo == (
unsigned)-1);
2647 int ARMAsmParser::tryParseRegister() {
2648 const AsmToken &Tok = Parser.getTok();
2655 .Case(
"r13", ARM::SP)
2656 .
Case(
"r14", ARM::LR)
2657 .
Case(
"r15", ARM::PC)
2658 .
Case(
"ip", ARM::R12)
2660 .
Case(
"a1", ARM::R0)
2661 .
Case(
"a2", ARM::R1)
2663 .
Case(
"a4", ARM::R3)
2665 .
Case(
"v2", ARM::R5)
2667 .
Case(
"v4", ARM::R7)
2668 .
Case(
"v5", ARM::R8)
2669 .
Case(
"v6", ARM::R9)
2670 .
Case(
"v7", ARM::R10)
2671 .
Case(
"v8", ARM::R11)
2672 .
Case(
"sb", ARM::R9)
2673 .
Case(
"sl", ARM::R10)
2674 .
Case(
"fp", ARM::R11)
2683 if (Entry == RegisterReqs.
end())
2686 return Entry->getValue();
2699 int ARMAsmParser::tryParseShiftRegister(
2701 SMLoc S = Parser.getTok().getLoc();
2702 const AsmToken &Tok = Parser.getTok();
2724 if (!PrevOp->isReg())
2725 return Error(PrevOp->getStartLoc(),
"shift must be of a register");
2726 int SrcReg = PrevOp->getReg();
2741 SMLoc ImmLoc = Parser.getTok().getLoc();
2742 const MCExpr *ShiftExpr = 0;
2743 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2744 Error(ImmLoc,
"invalid immediate shift value");
2750 Error(ImmLoc,
"invalid immediate shift value");
2760 Error(ImmLoc,
"immediate shift value out of range");
2768 SMLoc L = Parser.getTok().getLoc();
2769 EndLoc = Parser.getTok().getEndLoc();
2770 ShiftReg = tryParseRegister();
2771 if (ShiftReg == -1) {
2772 Error (L,
"expected immediate or register in shift operand");
2776 Error (Parser.getTok().getLoc(),
2777 "expected immediate or register in shift operand");
2783 Operands.
push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2787 Operands.
push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2802 const AsmToken &RegTok = Parser.getTok();
2803 int RegNo = tryParseRegister();
2810 const AsmToken &ExclaimTok = Parser.getTok();
2822 SMLoc SIdx = Parser.getTok().getLoc();
2826 if (getParser().parseExpression(ImmVal))
2830 return TokError(
"immediate value expected for vector index");
2833 return Error(Parser.getTok().getLoc(),
"']' expected");
2835 SMLoc E = Parser.getTok().getEndLoc();
2852 switch (Name.
size()) {
2855 if (Name[0] != CoprocOp)
2871 if (Name[0] != CoprocOp || Name[1] !=
'1')
2876 case '0':
return CoprocOp ==
'p'? -1: 10;
2877 case '1':
return CoprocOp ==
'p'? -1: 11;
2878 case '2':
return 12;
2879 case '3':
return 13;
2880 case '4':
return 14;
2881 case '5':
return 15;
2887 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2889 SMLoc S = Parser.getTok().getLoc();
2890 const AsmToken &Tok = Parser.getTok();
2892 return MatchOperand_NoMatch;
2913 return MatchOperand_NoMatch;
2918 return MatchOperand_Success;
2924 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2926 SMLoc S = Parser.getTok().getLoc();
2927 const AsmToken &Tok = Parser.getTok();
2929 return MatchOperand_NoMatch;
2933 return MatchOperand_NoMatch;
2936 Operands.
push_back(ARMOperand::CreateCoprocNum(Num, S));
2937 return MatchOperand_Success;
2943 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2945 SMLoc S = Parser.getTok().getLoc();
2946 const AsmToken &Tok = Parser.getTok();
2948 return MatchOperand_NoMatch;
2952 return MatchOperand_NoMatch;
2955 Operands.
push_back(ARMOperand::CreateCoprocReg(Reg, S));
2956 return MatchOperand_Success;
2961 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2963 SMLoc S = Parser.getTok().getLoc();
2967 return MatchOperand_NoMatch;
2971 SMLoc Loc = Parser.getTok().getLoc();
2972 if (getParser().parseExpression(Expr)) {
2973 Error(Loc,
"illegal expression");
2974 return MatchOperand_ParseFail;
2978 Error(Loc,
"coprocessor option must be an immediate in range [0, 255]");
2979 return MatchOperand_ParseFail;
2985 return MatchOperand_ParseFail;
2986 SMLoc E = Parser.getTok().getEndLoc();
2989 Operands.
push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2990 return MatchOperand_Success;
3000 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3004 case ARM::R0:
return ARM::R1;
case ARM::R1:
return ARM::R2;
3007 case ARM::R6:
return ARM::R7;
case ARM::R7:
return ARM::R8;
3008 case ARM::R8:
return ARM::R9;
case ARM::R9:
return ARM::R10;
3009 case ARM::R10:
return ARM::R11;
case ARM::R11:
return ARM::R12;
3010 case ARM::R12:
return ARM::SP;
case ARM::SP:
return ARM::LR;
3011 case ARM::LR:
return ARM::PC;
case ARM::PC:
return ARM::R0;
3019 case ARM::Q0:
return ARM::D0;
3020 case ARM::Q1:
return ARM::D2;
3021 case ARM::Q2:
return ARM::D4;
3022 case ARM::Q3:
return ARM::D6;
3024 case ARM::Q5:
return ARM::D10;
3025 case ARM::Q6:
return ARM::D12;
3026 case ARM::Q7:
return ARM::D14;
3027 case ARM::Q8:
return ARM::D16;
3028 case ARM::Q9:
return ARM::D18;
3029 case ARM::Q10:
return ARM::D20;
3030 case ARM::Q11:
return ARM::D22;
3031 case ARM::Q12:
return ARM::D24;
3032 case ARM::Q13:
return ARM::D26;
3033 case ARM::Q14:
return ARM::D28;
3034 case ARM::Q15:
return ARM::D30;
3042 "Token is not a Left Curly Brace");
3043 SMLoc S = Parser.getTok().getLoc();
3045 SMLoc RegLoc = Parser.getTok().getLoc();
3049 int Reg = tryParseRegister();
3051 return Error(RegLoc,
"register expected");
3059 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3062 Registers.
push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3066 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3067 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3068 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3069 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3070 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3071 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3073 return Error(RegLoc,
"invalid register in register list");
3077 Registers.
push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3086 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3087 int EndReg = tryParseRegister();
3089 return Error(AfterMinusLoc,
"register expected");
3091 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3099 return Error(AfterMinusLoc,
"invalid register in register list");
3102 return Error(AfterMinusLoc,
"bad range in register list");
3105 while (Reg != EndReg) {
3108 Registers.
push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3113 RegLoc = Parser.getTok().getLoc();
3115 const AsmToken RegTok = Parser.getTok();
3116 Reg = tryParseRegister();
3118 return Error(RegLoc,
"register expected");
3120 bool isQReg =
false;
3121 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3127 return Error(RegLoc,
"invalid register in register list");
3130 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3131 Warning(RegLoc,
"register list not in ascending order");
3133 return Error(RegLoc,
"register list not in ascending order");
3136 Warning(RegLoc,
"duplicated register (" + RegTok.
getString() +
3137 ") in register list");
3141 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3143 return Error(RegLoc,
"non-contiguous register range");
3145 Registers.
push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3148 Registers.
push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3153 return Error(Parser.getTok().getLoc(),
"'}' expected");
3154 SMLoc E = Parser.getTok().getEndLoc();
3158 Operands.
push_back(ARMOperand::CreateRegList(Registers, S, E));
3162 Operands.
push_back(ARMOperand::CreateToken(
"^",Parser.getTok().getLoc()));
3170 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3177 LaneKind = AllLanes;
3178 EndLoc = Parser.getTok().getEndLoc();
3180 return MatchOperand_Success;
3189 SMLoc Loc = Parser.getTok().getLoc();
3190 if (getParser().parseExpression(LaneIndex)) {
3191 Error(Loc,
"illegal expression");
3192 return MatchOperand_ParseFail;
3196 Error(Loc,
"lane index must be empty or an integer");
3197 return MatchOperand_ParseFail;
3200 Error(Parser.getTok().getLoc(),
"']' expected");
3201 return MatchOperand_ParseFail;
3203 EndLoc = Parser.getTok().getEndLoc();
3208 if (Val < 0 || Val > 7) {
3209 Error(Parser.getTok().getLoc(),
"lane index out of range");
3210 return MatchOperand_ParseFail;
3213 LaneKind = IndexedLane;
3214 return MatchOperand_Success;
3217 return MatchOperand_Success;
3221 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3225 SMLoc S = Parser.getTok().getLoc();
3230 SMLoc E = Parser.getTok().getEndLoc();
3231 int Reg = tryParseRegister();
3233 return MatchOperand_NoMatch;
3234 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3235 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3236 if (Res != MatchOperand_Success)
3240 Operands.
push_back(ARMOperand::CreateVectorList(Reg, 1,
false, S, E));
3243 Operands.
push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1,
false,
3247 Operands.
push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3252 return MatchOperand_Success;
3254 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3256 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3257 if (Res != MatchOperand_Success)
3262 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3263 Operands.
push_back(ARMOperand::CreateVectorList(Reg, 2,
false, S, E));
3267 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3268 Operands.
push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2,
false,
3272 Operands.
push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3277 return MatchOperand_Success;
3279 Error(S,
"vector register expected");
3280 return MatchOperand_ParseFail;
3284 return MatchOperand_NoMatch;
3287 SMLoc RegLoc = Parser.getTok().getLoc();
3289 int Reg = tryParseRegister();
3291 Error(RegLoc,
"register expected");
3292 return MatchOperand_ParseFail;
3296 unsigned FirstReg =
Reg;
3299 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3308 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3309 return MatchOperand_ParseFail;
3316 else if (Spacing == 2) {
3317 Error(Parser.getTok().getLoc(),
3318 "sequential registers in double spaced list");
3319 return MatchOperand_ParseFail;
3322 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3323 int EndReg = tryParseRegister();
3325 Error(AfterMinusLoc,
"register expected");
3326 return MatchOperand_ParseFail;
3329 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3336 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3337 Error(AfterMinusLoc,
"invalid register in register list");
3338 return MatchOperand_ParseFail;
3342 Error(AfterMinusLoc,
"bad range in register list");
3343 return MatchOperand_ParseFail;
3347 unsigned NextLaneIndex;
3348 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3349 MatchOperand_Success)
3350 return MatchOperand_ParseFail;
3351 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3352 Error(AfterMinusLoc,
"mismatched lane index in register list");
3353 return MatchOperand_ParseFail;
3357 Count += EndReg -
Reg;
3362 RegLoc = Parser.getTok().getLoc();
3364 Reg = tryParseRegister();
3366 Error(RegLoc,
"register expected");
3367 return MatchOperand_ParseFail;
3375 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3378 else if (Spacing == 2) {
3380 "invalid register in double-spaced list (must be 'D' register')");
3381 return MatchOperand_ParseFail;
3384 if (Reg != OldReg + 1) {
3385 Error(RegLoc,
"non-contiguous register range");
3386 return MatchOperand_ParseFail;
3392 unsigned NextLaneIndex;
3393 SMLoc LaneLoc = Parser.getTok().getLoc();
3394 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3395 MatchOperand_Success)
3396 return MatchOperand_ParseFail;
3397 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3398 Error(LaneLoc,
"mismatched lane index in register list");
3399 return MatchOperand_ParseFail;
3407 Spacing = 1 + (Reg == OldReg + 2);
3410 if (Reg != OldReg + Spacing) {
3411 Error(RegLoc,
"non-contiguous register range");
3412 return MatchOperand_ParseFail;
3417 unsigned NextLaneIndex;
3418 SMLoc EndLoc = Parser.getTok().getLoc();
3419 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3420 return MatchOperand_ParseFail;
3421 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3422 Error(EndLoc,
"mismatched lane index in register list");
3423 return MatchOperand_ParseFail;
3428 Error(Parser.getTok().getLoc(),
"'}' expected");
3429 return MatchOperand_ParseFail;
3431 E = Parser.getTok().getEndLoc();
3440 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3441 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3445 Operands.
push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3446 (Spacing == 2), S, E));
3453 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3454 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3457 Operands.
push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3462 Operands.
push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3468 return MatchOperand_Success;
3472 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3474 SMLoc S = Parser.getTok().getLoc();
3475 const AsmToken &Tok = Parser.getTok();
3506 return MatchOperand_NoMatch;
3514 SMLoc Loc = Parser.getTok().getLoc();
3516 const MCExpr *MemBarrierID;
3517 if (getParser().parseExpression(MemBarrierID)) {
3518 Error(Loc,
"illegal expression");
3519 return MatchOperand_ParseFail;
3524 Error(Loc,
"constant expression expected");
3525 return MatchOperand_ParseFail;
3530 Error(Loc,
"immediate value out of range");
3531 return MatchOperand_ParseFail;
3536 return MatchOperand_ParseFail;
3539 return MatchOperand_Success;
3543 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3545 SMLoc S = Parser.getTok().getLoc();
3546 const AsmToken &Tok = Parser.getTok();
3555 return MatchOperand_NoMatch;
3563 SMLoc Loc = Parser.getTok().getLoc();
3565 const MCExpr *ISBarrierID;
3566 if (getParser().parseExpression(ISBarrierID)) {
3567 Error(Loc,
"illegal expression");
3568 return MatchOperand_ParseFail;
3573 Error(Loc,
"constant expression expected");
3574 return MatchOperand_ParseFail;
3579 Error(Loc,
"immediate value out of range");
3580 return MatchOperand_ParseFail;
3585 return MatchOperand_ParseFail;
3587 Operands.
push_back(ARMOperand::CreateInstSyncBarrierOpt(
3589 return MatchOperand_Success;
3594 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3596 SMLoc S = Parser.getTok().getLoc();
3597 const AsmToken &Tok = Parser.getTok();
3599 return MatchOperand_NoMatch;
3604 unsigned IFlags = 0;
3605 if (IFlagsStr !=
"none") {
3606 for (
int i = 0, e = IFlagsStr.
size(); i != e; ++i) {
3615 if (Flag == ~0U || (IFlags & Flag))
3616 return MatchOperand_NoMatch;
3624 return MatchOperand_Success;
3628 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3630 SMLoc S = Parser.getTok().getLoc();
3631 const AsmToken &Tok = Parser.getTok();
3633 return MatchOperand_NoMatch;
3653 .Case(
"apsr", 0x800)
3654 .
Case(
"apsr_nzcvq", 0x800)
3655 .
Case(
"apsr_g", 0x400)
3656 .
Case(
"apsr_nzcvqg", 0xc00)
3657 .
Case(
"iapsr", 0x801)
3658 .
Case(
"iapsr_nzcvq", 0x801)
3659 .
Case(
"iapsr_g", 0x401)
3660 .
Case(
"iapsr_nzcvqg", 0xc01)
3661 .
Case(
"eapsr", 0x802)
3662 .
Case(
"eapsr_nzcvq", 0x802)
3663 .
Case(
"eapsr_g", 0x402)
3664 .
Case(
"eapsr_nzcvqg", 0xc02)
3665 .
Case(
"xpsr", 0x803)
3666 .
Case(
"xpsr_nzcvq", 0x803)
3667 .
Case(
"xpsr_g", 0x403)
3668 .
Case(
"xpsr_nzcvqg", 0xc03)
3669 .
Case(
"ipsr", 0x805)
3670 .
Case(
"epsr", 0x806)
3671 .
Case(
"iepsr", 0x807)
3674 .
Case(
"primask", 0x810)
3675 .
Case(
"basepri", 0x811)
3676 .
Case(
"basepri_max", 0x812)
3677 .
Case(
"faultmask", 0x813)
3678 .
Case(
"control", 0x814)
3681 if (FlagsVal == ~0U)
3682 return MatchOperand_NoMatch;
3684 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3686 return MatchOperand_NoMatch;
3689 Operands.
push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3690 return MatchOperand_Success;
3694 size_t Start = 0, Next = Mask.
find(
'_');
3696 std::string SpecReg = Mask.
slice(Start, Next).
lower();
3698 Flags = Mask.
slice(Next+1, Mask.
size());
3703 unsigned FlagsVal = 0;
3705 if (SpecReg ==
"apsr") {
3709 .
Case(
"nzcvqg", 0xc)
3712 if (FlagsVal == ~0U) {
3714 return MatchOperand_NoMatch;
3718 }
else if (SpecReg ==
"cpsr" || SpecReg ==
"spsr") {
3720 if (Flags ==
"all" || Flags ==
"")
3722 for (
int i = 0, e = Flags.
size(); i != e; ++i) {
3732 if (FlagsVal == ~0U || (FlagsVal & Flag))
3733 return MatchOperand_NoMatch;
3737 return MatchOperand_NoMatch;
3748 if (SpecReg ==
"spsr")
3752 Operands.
push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3753 return MatchOperand_Success;
3756 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3758 int Low,
int High) {
3759 const AsmToken &Tok = Parser.getTok();
3761 Error(Parser.getTok().getLoc(), Op +
" operand expected.");
3762 return MatchOperand_ParseFail;
3765 std::string LowerOp = Op.
lower();
3766 std::string UpperOp = Op.
upper();
3767 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3768 Error(Parser.getTok().getLoc(), Op +
" operand expected.");
3769 return MatchOperand_ParseFail;
3776 Error(Parser.getTok().getLoc(),
"'#' expected");
3777 return MatchOperand_ParseFail;
3781 const MCExpr *ShiftAmount;
3782 SMLoc Loc = Parser.getTok().getLoc();
3784 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3785 Error(Loc,
"illegal expression");
3786 return MatchOperand_ParseFail;
3790 Error(Loc,
"constant expression expected");
3791 return MatchOperand_ParseFail;
3794 if (Val < Low || Val > High) {
3795 Error(Loc,
"immediate value out of range");
3796 return MatchOperand_ParseFail;
3799 Operands.
push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3801 return MatchOperand_Success;
3804 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3806 const AsmToken &Tok = Parser.getTok();
3809 Error(S,
"'be' or 'le' operand expected");
3810 return MatchOperand_ParseFail;
3819 Error(S,
"'be' or 'le' operand expected");
3820 return MatchOperand_ParseFail;
3825 return MatchOperand_Success;
3833 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3835 const AsmToken &Tok = Parser.getTok();
3838 Error(S,
"shift operator 'asr' or 'lsl' expected");
3839 return MatchOperand_ParseFail;
3843 if (ShiftName ==
"lsl" || ShiftName ==
"LSL")
3845 else if (ShiftName ==
"asr" || ShiftName ==
"ASR")
3848 Error(S,
"shift operator 'asr' or 'lsl' expected");
3849 return MatchOperand_ParseFail;
3856 Error(Parser.getTok().getLoc(),
"'#' expected");
3857 return MatchOperand_ParseFail;
3860 SMLoc ExLoc = Parser.getTok().getLoc();
3862 const MCExpr *ShiftAmount;
3864 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3865 Error(ExLoc,
"malformed shift expression");
3866 return MatchOperand_ParseFail;
3870 Error(ExLoc,
"shift amount must be an immediate");
3871 return MatchOperand_ParseFail;
3877 if (Val < 1 || Val > 32) {
3878 Error(ExLoc,
"'asr' shift amount must be in range [1,32]");
3879 return MatchOperand_ParseFail;
3882 if (isThumb() && Val == 32) {
3883 Error(ExLoc,
"'asr #32' shift amount not allowed in Thumb mode");
3884 return MatchOperand_ParseFail;
3886 if (Val == 32) Val = 0;
3889 if (Val < 0 || Val > 31) {
3890 Error(ExLoc,
"'lsr' shift amount must be in range [0,31]");
3891 return MatchOperand_ParseFail;
3895 Operands.
push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3897 return MatchOperand_Success;
3903 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3905 const AsmToken &Tok = Parser.getTok();
3908 return MatchOperand_NoMatch;
3910 if (ShiftName !=
"ror" && ShiftName !=
"ROR")
3911 return MatchOperand_NoMatch;
3917 Error(Parser.getTok().getLoc(),
"'#' expected");
3918 return MatchOperand_ParseFail;
3921 SMLoc ExLoc = Parser.getTok().getLoc();
3923 const MCExpr *ShiftAmount;
3925 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3926 Error(ExLoc,
"malformed rotate expression");
3927 return MatchOperand_ParseFail;
3931 Error(ExLoc,
"rotate amount must be an immediate");
3932 return MatchOperand_ParseFail;
3939 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3940 Error(ExLoc,
"'ror' rotate amount must be 8, 16, or 24");
3941 return MatchOperand_ParseFail;
3944 Operands.
push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3946 return MatchOperand_Success;
3949 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3951 SMLoc S = Parser.getTok().getLoc();
3955 Error(Parser.getTok().getLoc(),
"'#' expected");
3956 return MatchOperand_ParseFail;
3961 SMLoc E = Parser.getTok().getLoc();
3962 if (getParser().parseExpression(LSBExpr)) {
3963 Error(E,
"malformed immediate expression");
3964 return MatchOperand_ParseFail;
3968 Error(E,
"'lsb' operand must be an immediate");
3969 return MatchOperand_ParseFail;
3974 if (LSB < 0 || LSB > 31) {
3975 Error(E,
"'lsb' operand must be in the range [0,31]");
3976 return MatchOperand_ParseFail;
3978 E = Parser.getTok().getLoc();
3982 Error(Parser.getTok().getLoc(),
"too few operands");
3983 return MatchOperand_ParseFail;
3988 Error(Parser.getTok().getLoc(),
"'#' expected");
3989 return MatchOperand_ParseFail;
3995 if (getParser().parseExpression(WidthExpr, EndLoc)) {
3996 Error(E,
"malformed immediate expression");
3997 return MatchOperand_ParseFail;
4001 Error(E,
"'width' operand must be an immediate");
4002 return MatchOperand_ParseFail;
4007 if (Width < 1 || Width > 32 - LSB) {
4008 Error(E,
"'width' operand must be in the range [1,32-lsb]");
4009 return MatchOperand_ParseFail;
4012 Operands.
push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4014 return MatchOperand_Success;
4017 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4029 bool haveEaten =
false;
4040 SMLoc E = Parser.getTok().getEndLoc();
4041 int Reg = tryParseRegister();
4044 return MatchOperand_NoMatch;
4045 Error(Parser.getTok().getLoc(),
"register expected");
4046 return MatchOperand_ParseFail;
4050 unsigned ShiftImm = 0;
4053 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4054 return MatchOperand_ParseFail;
4057 E = Parser.getTok().getLoc();
4060 Operands.
push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4063 return MatchOperand_Success;
4066 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4091 if (getParser().parseExpression(Offset, E))
4092 return MatchOperand_ParseFail;
4095 Error(S,
"constant expression expected");
4096 return MatchOperand_ParseFail;
4100 if (isNegative && Val == 0)
4106 return MatchOperand_Success;
4110 bool haveEaten =
false;
4121 Tok = Parser.getTok();
4122 int Reg = tryParseRegister();
4125 return MatchOperand_NoMatch;
4127 return MatchOperand_ParseFail;
4133 return MatchOperand_Success;
4140 cvtThumbMultiply(
MCInst &Inst,
4142 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4143 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4147 if (Operands.
size() == 6 &&
4148 ((ARMOperand*)Operands[4])->getReg() ==
4149 ((ARMOperand*)Operands[3])->getReg())
4151 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4153 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4157 cvtThumbBranches(
MCInst &Inst,
4159 int CondOp = -1, ImmOp = -1;
4162 case ARM::tBcc: CondOp = 1; ImmOp = 2;
break;
4165 case ARM::t2Bcc: CondOp = 1; ImmOp = 3;
break;
4175 case ARM::tBcc: Inst.
setOpcode(ARM::tB);
break;
4176 case ARM::t2Bcc: Inst.
setOpcode(ARM::t2B);
break;
4181 unsigned Cond =
static_cast<ARMOperand*
>(Operands[CondOp])->getCondCode();
4198 ARMOperand* op =
static_cast<ARMOperand*
>(Operands[ImmOp]);
4199 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4205 ARMOperand* op =
static_cast<ARMOperand*
>(Operands[ImmOp]);
4206 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4211 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4212 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4221 "Token is not a Left Bracket");
4222 S = Parser.getTok().getLoc();
4225 const AsmToken &BaseRegTok = Parser.getTok();
4226 int BaseRegNum = tryParseRegister();
4227 if (BaseRegNum == -1)
4228 return Error(BaseRegTok.
getLoc(),
"register expected");
4231 const AsmToken &Tok = Parser.getTok();
4234 return Error(Tok.getLoc(),
"malformed memory operand");
4237 E = Tok.getEndLoc();
4241 0, 0,
false, S, E));
4246 Operands.
push_back(ARMOperand::CreateToken(
"!",Parser.getTok().getLoc()));
4254 "Lost colon or comma in memory operand?!");
4262 E = Parser.getTok().getLoc();
4265 if (getParser().parseExpression(Expr))
4273 return Error (E,
"constant expression expected");
4279 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4280 case 16: Align = 2;
break;
4281 case 32: Align = 4;
break;
4282 case 64: Align = 8;
break;
4283 case 128: Align = 16;
break;
4284 case 256: Align = 32;
break;
4289 return Error(Parser.getTok().getLoc(),
"']' expected");
4290 E = Parser.getTok().getEndLoc();
4295 Operands.
push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4302 Operands.
push_back(ARMOperand::CreateToken(
"!",Parser.getTok().getLoc()));
4317 E = Parser.getTok().getLoc();
4321 if (getParser().parseExpression(Offset))
4329 return Error (E,
"constant expression expected");
4333 if (isNegative && Val == 0)
4338 return Error(Parser.getTok().getLoc(),
"']' expected");
4339 E = Parser.getTok().getEndLoc();
4344 Operands.
push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4351 Operands.
push_back(ARMOperand::CreateToken(
"!",Parser.getTok().getLoc()));
4359 bool isNegative =
false;
4368 E = Parser.getTok().getLoc();
4369 int OffsetRegNum = tryParseRegister();
4370 if (OffsetRegNum == -1)
4371 return Error(E,
"register expected");
4375 unsigned ShiftImm = 0;
4378 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4384 return Error(Parser.getTok().getLoc(),
"']' expected");
4385 E = Parser.getTok().getEndLoc();
4388 Operands.
push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4389 ShiftType, ShiftImm, 0, isNegative,
4395 Operands.
push_back(ARMOperand::CreateToken(
"!",Parser.getTok().getLoc()));
4408 SMLoc Loc = Parser.getTok().getLoc();
4409 const AsmToken &Tok = Parser.getTok();
4413 if (ShiftName ==
"lsl" || ShiftName ==
"LSL" ||
4414 ShiftName ==
"asl" || ShiftName ==
"ASL")
4416 else if (ShiftName ==
"lsr" || ShiftName ==
"LSR")
4418 else if (ShiftName ==
"asr" || ShiftName ==
"ASR")
4420 else if (ShiftName ==
"ror" || ShiftName ==
"ROR")
4422 else if (ShiftName ==
"rrx" || ShiftName ==
"RRX")
4425 return Error(Loc,
"illegal shift operator");
4431 Loc = Parser.getTok().getLoc();
4433 const AsmToken &HashTok = Parser.getTok();
4440 if (getParser().parseExpression(Expr))
4447 return Error(Loc,
"shift amount must be an immediate");
4452 return Error(Loc,
"immediate shift value out of range");
4466 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4477 SMLoc S = Parser.getTok().getLoc();
4481 return MatchOperand_NoMatch;
4493 ARMOperand *TyOp =
static_cast<ARMOperand*
>(Operands[2]);
4494 if (!TyOp->isToken() || (TyOp->getToken() !=
".f32" &&
4495 TyOp->getToken() !=
".f64"))
4496 return MatchOperand_NoMatch;
4501 bool isNegative =
false;
4506 const AsmToken &Tok = Parser.getTok();
4510 uint64_t
IntVal = RealVal.bitcastToAPInt().getZExtValue();
4512 IntVal ^= (uint64_t)isNegative << 31;
4514 Operands.
push_back(ARMOperand::CreateImm(
4516 S, Parser.getTok().getLoc()));
4517 return MatchOperand_Success;
4524 if (Val > 255 || Val < 0) {
4525 Error(Loc,
"encoded floating point value out of range");
4526 return MatchOperand_ParseFail;
4530 Operands.
push_back(ARMOperand::CreateImm(
4532 Parser.getTok().getLoc()));
4533 return MatchOperand_Success;
4536 Error(Loc,
"invalid floating point immediate");
4537 return MatchOperand_ParseFail;
4548 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4549 if (ResTy == MatchOperand_Success)
4554 if (ResTy == MatchOperand_ParseFail)
4557 switch (getLexer().getKind()) {
4559 Error(Parser.getTok().getLoc(),
"unexpected token in operand");
4565 bool ExpectLabel = Mnemonic ==
"b" || Mnemonic ==
"bl";
4567 if (!tryParseRegisterWithWriteBack(Operands))
4569 int Res = tryParseShiftRegister(Operands);
4575 if (Mnemonic ==
"vmrs" &&
4576 Parser.getTok().getString().
equals_lower(
"apsr_nzcv")) {
4577 S = Parser.getTok().getLoc();
4579 Operands.
push_back(ARMOperand::CreateToken(
"APSR_nzcv", S));
4594 S = Parser.getTok().getLoc();
4595 if (getParser().parseExpression(IdVal))
4598 Operands.
push_back(ARMOperand::CreateImm(IdVal, S, E));
4602 return parseMemory(Operands);
4604 return parseRegisterList(Operands);
4608 S = Parser.getTok().getLoc();
4614 if (getParser().parseExpression(ImmVal))
4619 if (isNegative && Val == 0)
4623 Operands.
push_back(ARMOperand::CreateImm(ImmVal, S, E));
4629 Operands.
push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4630 Parser.getTok().getLoc()));
4643 if (parsePrefix(RefKind))
4646 const MCExpr *SubExprVal;
4647 if (getParser().parseExpression(SubExprVal))
4653 Operands.
push_back(ARMOperand::CreateImm(ExprVal, S, E));
4669 Error(Parser.getTok().getLoc(),
"expected prefix identifier in operand");
4673 StringRef IDVal = Parser.getTok().getIdentifier();
4674 if (IDVal ==
"lower16") {
4676 }
else if (IDVal ==
"upper16") {
4679 Error(Parser.getTok().getLoc(),
"unexpected prefix in operand");
4685 Error(Parser.getTok().getLoc(),
"unexpected token after prefix");
4698 unsigned &PredicationCode,
4700 unsigned &ProcessorIMod,
4703 CarrySetting =
false;
4709 if ((Mnemonic ==
"movs" && isThumb()) ||
4710 Mnemonic ==
"teq" || Mnemonic ==
"vceq" || Mnemonic ==
"svc" ||
4711 Mnemonic ==
"mls" || Mnemonic ==
"smmls" || Mnemonic ==
"vcls" ||
4712 Mnemonic ==
"vmls" || Mnemonic ==
"vnmls" || Mnemonic ==
"vacge" ||
4713 Mnemonic ==
"vcge" || Mnemonic ==
"vclt" || Mnemonic ==
"vacgt" ||
4714 Mnemonic ==
"vaclt" || Mnemonic ==
"vacle" || Mnemonic ==
"hlt" ||
4715 Mnemonic ==
"vcgt" || Mnemonic ==
"vcle" || Mnemonic ==
"smlal" ||
4716 Mnemonic ==
"umaal" || Mnemonic ==
"umlal" || Mnemonic ==
"vabal" ||
4717 Mnemonic ==
"vmlal" || Mnemonic ==
"vpadal" || Mnemonic ==
"vqdmlal" ||
4718 Mnemonic ==
"fmuls" || Mnemonic ==
"vmaxnm" || Mnemonic ==
"vminnm" ||
4719 Mnemonic ==
"vcvta" || Mnemonic ==
"vcvtn" || Mnemonic ==
"vcvtp" ||
4720 Mnemonic ==
"vcvtm" || Mnemonic ==
"vrinta" || Mnemonic ==
"vrintn" ||
4721 Mnemonic ==
"vrintp" || Mnemonic ==
"vrintm" || Mnemonic.
startswith(
"vsel"))
4726 if (Mnemonic !=
"adcs" && Mnemonic !=
"bics" && Mnemonic !=
"movs" &&
4727 Mnemonic !=
"muls" && Mnemonic !=
"smlals" && Mnemonic !=
"smulls" &&
4728 Mnemonic !=
"umlals" && Mnemonic !=
"umulls" && Mnemonic !=
"lsls" &&
4729 Mnemonic !=
"sbcs" && Mnemonic !=
"rscs") {
4750 Mnemonic = Mnemonic.
slice(0, Mnemonic.
size() - 2);
4751 PredicationCode = CC;
4758 !(Mnemonic ==
"cps" || Mnemonic ==
"mls" ||
4759 Mnemonic ==
"mrs" || Mnemonic ==
"smmls" || Mnemonic ==
"vabs" ||
4760 Mnemonic ==
"vcls" || Mnemonic ==
"vmls" || Mnemonic ==
"vmrs" ||
4761 Mnemonic ==
"vnmls" || Mnemonic ==
"vqabs" || Mnemonic ==
"vrecps" ||
4762 Mnemonic ==
"vrsqrts" || Mnemonic ==
"srs" || Mnemonic ==
"flds" ||
4763 Mnemonic ==
"fmrs" || Mnemonic ==
"fsqrts" || Mnemonic ==
"fsubs" ||
4764 Mnemonic ==
"fsts" || Mnemonic ==
"fcpys" || Mnemonic ==
"fdivs" ||
4765 Mnemonic ==
"fmuls" || Mnemonic ==
"fcmps" || Mnemonic ==
"fcmpzs" ||
4766 Mnemonic ==
"vfms" || Mnemonic ==
"vfnms" ||
4767 (Mnemonic ==
"movs" && isThumb()))) {
4768 Mnemonic = Mnemonic.
slice(0, Mnemonic.
size() - 1);
4769 CarrySetting =
true;
4782 Mnemonic = Mnemonic.
slice(0, Mnemonic.
size()-2);
4783 ProcessorIMod =
IMod;
4789 ITMask = Mnemonic.
slice(2, Mnemonic.
size());
4790 Mnemonic = Mnemonic.
slice(0, 2);
4802 bool &CanAcceptCarrySet,
bool &CanAcceptPredicationCode) {
4803 if (Mnemonic ==
"and" || Mnemonic ==
"lsl" || Mnemonic ==
"lsr" ||
4804 Mnemonic ==
"rrx" || Mnemonic ==
"ror" || Mnemonic ==
"sub" ||
4805 Mnemonic ==
"add" || Mnemonic ==
"adc" ||
4806 Mnemonic ==
"mul" || Mnemonic ==
"bic" || Mnemonic ==
"asr" ||
4807 Mnemonic ==
"orr" || Mnemonic ==
"mvn" ||
4808 Mnemonic ==
"rsb" || Mnemonic ==
"rsc" || Mnemonic ==
"orn" ||
4809 Mnemonic ==
"sbc" || Mnemonic ==
"eor" || Mnemonic ==
"neg" ||
4810 Mnemonic ==
"vfm" || Mnemonic ==
"vfnm" ||
4811 (!isThumb() && (Mnemonic ==
"smull" || Mnemonic ==
"mov" ||
4812 Mnemonic ==
"mla" || Mnemonic ==
"smlal" ||
4813 Mnemonic ==
"umlal" || Mnemonic ==
"umull"))) {
4814 CanAcceptCarrySet =
true;
4816 CanAcceptCarrySet =
false;
4818 if (Mnemonic ==
"bkpt" || Mnemonic ==
"cbnz" || Mnemonic ==
"setend" ||
4819 Mnemonic ==
"cps" || Mnemonic ==
"it" || Mnemonic ==
"cbz" ||
4820 Mnemonic ==
"trap" || Mnemonic ==
"hlt" || Mnemonic.
startswith(
"crc32") ||
4822 Mnemonic ==
"vmaxnm" || Mnemonic ==
"vminnm" || Mnemonic ==
"vcvta" ||
4823 Mnemonic ==
"vcvtn" || Mnemonic ==
"vcvtp" || Mnemonic ==
"vcvtm" ||
4824 Mnemonic ==
"vrinta" || Mnemonic ==
"vrintn" || Mnemonic ==
"vrintp" ||
4825 Mnemonic ==
"vrintm" || Mnemonic.
startswith(
"aes") ||
4829 CanAcceptPredicationCode =
false;
4830 }
else if (!isThumb()) {
4832 CanAcceptPredicationCode
4833 = Mnemonic !=
"cdp2" && Mnemonic !=
"clrex" && Mnemonic !=
"mcr2" &&
4834 Mnemonic !=
"mcrr2" && Mnemonic !=
"mrc2" && Mnemonic !=
"mrrc2" &&
4835 Mnemonic !=
"dmb" && Mnemonic !=
"dsb" && Mnemonic !=
"isb" &&
4836 Mnemonic !=
"pld" && Mnemonic !=
"pli" && Mnemonic !=
"pldw" &&
4837 Mnemonic !=
"ldc2" && Mnemonic !=
"ldc2l" &&
4838 Mnemonic !=
"stc2" && Mnemonic !=
"stc2l" &&
4840 }
else if (isThumbOne()) {
4842 CanAcceptPredicationCode = Mnemonic !=
"movs";
4844 CanAcceptPredicationCode = Mnemonic !=
"nop" && Mnemonic !=
"movs";
4846 CanAcceptPredicationCode =
true;
4849 bool ARMAsmParser::shouldOmitCCOutOperand(
StringRef Mnemonic,
4862 if (Mnemonic ==
"mov" && Operands.
size() > 4 && !isThumb() &&
4863 !
static_cast<ARMOperand*
>(Operands[4])->isARMSOImm() &&
4864 static_cast<ARMOperand*
>(Operands[4])->isImm0_65535Expr() &&
4865 static_cast<ARMOperand*
>(Operands[1])->
getReg() == 0)
4870 if (isThumb() && Mnemonic ==
"add" && Operands.
size() == 5 &&
4871 static_cast<ARMOperand*
>(Operands[3])->
isReg() &&
4872 static_cast<ARMOperand*
>(Operands[4])->
isReg() &&
4873 static_cast<ARMOperand*
>(Operands[1])->
getReg() == 0)
4879 if (((isThumb() && Mnemonic ==
"add") ||
4880 (isThumbTwo() && Mnemonic ==
"sub")) &&
4881 Operands.
size() == 6 &&
4882 static_cast<ARMOperand*
>(Operands[3])->
isReg() &&
4883 static_cast<ARMOperand*
>(Operands[4])->
isReg() &&
4884 static_cast<ARMOperand*
>(Operands[4])->
getReg() == ARM::SP &&
4885 static_cast<ARMOperand*
>(Operands[1])->
getReg() == 0 &&
4886 ((Mnemonic ==
"add" &&
static_cast<ARMOperand*
>(Operands[5])->
isReg()) ||
4887 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4894 if (isThumbTwo() && (Mnemonic ==
"add" || Mnemonic ==
"sub") &&
4895 Operands.
size() == 6 &&
4896 static_cast<ARMOperand*
>(Operands[3])->
isReg() &&
4897 static_cast<ARMOperand*
>(Operands[4])->
isReg() &&
4898 static_cast<ARMOperand*
>(Operands[5])->isImm()) {
4906 static_cast<ARMOperand*
>(Operands[5])->isImm0_7())
4910 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4911 static_cast<ARMOperand*
>(Operands[5])->isT2SOImm())
4922 if (isThumbTwo() && Mnemonic ==
"mul" && Operands.
size() == 6 &&
4923 static_cast<ARMOperand*
>(Operands[1])->
getReg() == 0 &&
4924 static_cast<ARMOperand*
>(Operands[3])->
isReg() &&
4925 static_cast<ARMOperand*
>(Operands[4])->
isReg() &&
4926 static_cast<ARMOperand*
>(Operands[5])->
isReg() &&
4935 (
static_cast<ARMOperand*
>(Operands[3])->
getReg() !=
4936 static_cast<ARMOperand*
>(Operands[5])->
getReg() &&
4937 static_cast<ARMOperand*
>(Operands[3])->
getReg() !=
4938 static_cast<ARMOperand*
>(Operands[4])->
getReg())))
4943 if (isThumbTwo() && Mnemonic ==
"mul" && Operands.
size() == 5 &&
4944 static_cast<ARMOperand*
>(Operands[1])->
getReg() == 0 &&
4945 static_cast<ARMOperand*
>(Operands[3])->
isReg() &&
4946 static_cast<ARMOperand*
>(Operands[4])->
isReg() &&
4962 if (isThumb() && (Mnemonic ==
"add" || Mnemonic ==
"sub") &&
4963 (Operands.
size() == 5 || Operands.
size() == 6) &&
4964 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4965 static_cast<ARMOperand*
>(Operands[3])->
getReg() == ARM::SP &&
4966 static_cast<ARMOperand*
>(Operands[1])->
getReg() == 0 &&
4967 (
static_cast<ARMOperand*
>(Operands[4])->isImm() ||
4968 (Operands.
size() == 6 &&
4969 static_cast<ARMOperand*
>(Operands[5])->isImm())))
4975 bool ARMAsmParser::shouldOmitPredicateOperand(
4978 unsigned RegIdx = 3;
4979 if ((Mnemonic ==
"vrintz" || Mnemonic ==
"vrintx" || Mnemonic ==
"vrintr") &&
4980 static_cast<ARMOperand *>(Operands[2])->
getToken() ==
".f32") {
4981 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4982 static_cast<ARMOperand *>(Operands[3])->
getToken() ==
".f32")
4985 if (static_cast<ARMOperand *>(Operands[RegIdx])->
isReg() &&
4986 (ARMMCRegisterClasses[ARM::DPRRegClassID]
4987 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->
getReg()) ||
4988 ARMMCRegisterClasses[ARM::QPRRegClassID]
4989 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->
getReg())))
4996 return Tok ==
".8" || Tok ==
".16" || Tok ==
".32" || Tok ==
".64" ||
4997 Tok ==
".i8" || Tok ==
".i16" || Tok ==
".i32" || Tok ==
".i64" ||
4998 Tok ==
".u8" || Tok ==
".u16" || Tok ==
".u32" || Tok ==
".u64" ||
4999 Tok ==
".s8" || Tok ==
".s16" || Tok ==
".s32" || Tok ==
".s64" ||
5000 Tok ==
".p8" || Tok ==
".p16" || Tok ==
".f32" || Tok ==
".f64" ||
5001 Tok ==
".f" || Tok ==
".d";
5011 unsigned VariantID);
5021 unsigned AvailableFeatures = getAvailableFeatures();
5022 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5027 Parser.getTok().getIdentifier() ==
".req") {
5028 parseDirectiveReq(Name, NameLoc);
5035 size_t Start = 0, Next = Name.
find(
'.');
5039 unsigned PredicationCode;
5040 unsigned ProcessorIMod;
5043 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5044 ProcessorIMod, ITMask);
5047 if (isThumbOne() && PredicationCode !=
ARMCC::AL && Mnemonic !=
"b") {
5048 Parser.eatToEndOfStatement();
5049 return Error(NameLoc,
"conditional execution not supported in Thumb1");
5052 Operands.
push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5059 if (Mnemonic ==
"it") {
5061 if (ITMask.
size() > 3) {
5062 Parser.eatToEndOfStatement();
5063 return Error(Loc,
"too many conditions on IT instruction");
5066 for (
unsigned i = ITMask.
size(); i != 0; --i) {
5067 char pos = ITMask[i - 1];
5068 if (pos !=
't' && pos !=
'e') {
5069 Parser.eatToEndOfStatement();
5070 return Error(Loc,
"illegal IT block condition mask '" + ITMask +
"'");
5073 if (ITMask[i - 1] ==
't')
5076 Operands.
push_back(ARMOperand::CreateITMask(Mask, Loc));
5089 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5090 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5094 if (!CanAcceptCarrySet && CarrySetting) {
5095 Parser.eatToEndOfStatement();
5096 return Error(NameLoc,
"instruction '" + Mnemonic +
5097 "' can not set flags, but 's' suffix specified");
5101 if (!CanAcceptPredicationCode && PredicationCode !=
ARMCC::AL) {
5102 Parser.eatToEndOfStatement();
5103 return Error(NameLoc,
"instruction '" + Mnemonic +
5104 "' is not predicable, but condition code specified");
5108 if (CanAcceptCarrySet) {
5110 Operands.
push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5115 if (CanAcceptPredicationCode) {
5118 Operands.
push_back(ARMOperand::CreateCondCode(
5123 if (ProcessorIMod) {
5124 Operands.
push_back(ARMOperand::CreateImm(
5132 Next = Name.
find(
'.', Start + 1);
5142 if (ExtraToken ==
".n" && !isThumb()) {
5144 return Error(Loc,
"instruction with .n (narrow) qualifier not allowed in "
5151 if (ExtraToken !=
".n" && (isThumb() || ExtraToken !=
".w")) {
5153 Operands.
push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5160 if (parseOperand(Operands, Mnemonic)) {
5161 Parser.eatToEndOfStatement();
5169 if (parseOperand(Operands, Mnemonic)) {
5170 Parser.eatToEndOfStatement();
5177 SMLoc Loc = getLexer().getLoc();
5178 Parser.eatToEndOfStatement();
5179 return Error(Loc,
"unexpected token in argument list");
5191 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5192 ARMOperand *Op =
static_cast<ARMOperand*
>(Operands[1]);
5200 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5201 ARMOperand *Op =
static_cast<ARMOperand*
>(Operands[1]);
5211 if (!isThumb() && Mnemonic ==
"blx" && Operands.
size() == 3 &&
5212 static_cast<ARMOperand*
>(Operands[2])->isImm()) {
5213 ARMOperand *Op =
static_cast<ARMOperand*
>(Operands[1]);
5224 if (!isThumb() && Operands.
size() > 4 &&
5225 (Mnemonic ==
"ldrexd" || Mnemonic ==
"strexd" || Mnemonic ==
"ldaexd" ||
5226 Mnemonic ==
"stlexd")) {
5227 bool isLoad = (Mnemonic ==
"ldrexd" || Mnemonic ==
"ldaexd");
5228 unsigned Idx = isLoad ? 2 : 3;
5229 ARMOperand* Op1 =
static_cast<ARMOperand*
>(Operands[Idx]);
5230 ARMOperand* Op2 =
static_cast<ARMOperand*
>(Operands[Idx+1]);
5234 if (Op1->isReg() && Op2->isReg() && MRC.
contains(Op1->getReg()) &&
5236 unsigned Reg1 = Op1->getReg();
5237 unsigned Reg2 = Op2->getReg();
5242 if (Rt + 1 != Rt2 || (Rt & 1)) {
5243 Error(Op2->getStartLoc(), isLoad ?
5244 "destination operands must be sequential" :
5245 "source operands must be sequential");
5251 Operands.
insert(Operands.
begin() + Idx, ARMOperand::CreateReg(
5252 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5263 if (isThumbTwo() && Mnemonic ==
"sub" && Operands.
size() == 6 &&
5264 static_cast<ARMOperand*
>(Operands[3])->
isReg() &&
5265 static_cast<ARMOperand*
>(Operands[3])->
getReg() == ARM::PC &&
5266 static_cast<ARMOperand*
>(Operands[4])->
isReg() &&
5267 static_cast<ARMOperand*
>(Operands[4])->
getReg() == ARM::LR &&
5268 static_cast<ARMOperand*
>(Operands[5])->isImm()) {
5269 ARMOperand *Op0 =
static_cast<ARMOperand*
>(Operands[0]);
5272 Operands.
insert(Operands.
begin(), ARMOperand::CreateToken(Name, NameLoc));
5274 ARMOperand *Op1 =
static_cast<ARMOperand*
>(Operands[1]);
5288 containsReg =
false;
5314 return Inst.
getOpcode() == ARM::tBKPT ||
5323 validateInstruction(
MCInst &Inst,
5326 SMLoc Loc = Operands[0]->getStartLoc();
5333 if (ITState.FirstCond)
5334 ITState.FirstCond =
false;
5336 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5339 return Error(Loc,
"instructions in IT block must be predicable");
5341 unsigned ITCond = Bit ? ITState.Cond :
5343 if (Cond != ITCond) {
5346 for (
unsigned I = 1;
I < Operands.
size(); ++
I)
5347 if (static_cast<ARMOperand*>(Operands[
I])->isCondCode())
5348 CondLoc = Operands[I]->getStartLoc();
5349 return Error(CondLoc,
"incorrect condition in IT block; got '" +
5351 "', but expected '" +
5359 return Error(Loc,
"predicated instructions must be in IT block");
5361 const unsigned Opcode = Inst.
getOpcode();
5365 case ARM::LDRD_POST: {
5369 if (RtReg == ARM::LR)
5370 return Error(Operands[3]->getStartLoc(),
5376 return Error(Operands[3]->getStartLoc(),
5377 "Rt must be even-numbered");
5382 return Error(Operands[3]->getStartLoc(),
5383 "destination operands must be sequential");
5385 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5389 if (Rn == Rt || Rn == Rt2)
5390 return Error(Operands[3]->getStartLoc(),
5391 "base register needs to be different from destination "
5398 case ARM::t2LDRD_PRE:
5399 case ARM::t2LDRD_POST: {
5404 return Error(Operands[3]->getStartLoc(),
5405 "destination operands can't be identical");
5413 return Error(Operands[3]->getStartLoc(),
5414 "source operands must be sequential");
5418 case ARM::STRD_POST: {
5423 return Error(Operands[3]->getStartLoc(),
5424 "source operands must be sequential");
5432 if (Widthm1 >= 32 - LSB)
5433 return Error(Operands[5]->getStartLoc(),
5434 "bitfield width must be in range [1,32-lsb]");
5446 bool HasWritebackToken =
5447 (
static_cast<ARMOperand*
>(Operands[3])->isToken() &&
5448 static_cast<ARMOperand*
>(Operands[3])->
getToken() ==
"!");
5449 bool ListContainsBase;
5451 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5452 "registers must be in range r0-r7");
5454 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5455 return Error(Operands[2]->getStartLoc(),
5456 "writeback operator '!' expected");
5459 if (ListContainsBase && HasWritebackToken)
5460 return Error(Operands[3]->getStartLoc(),
5461 "writeback operator '!' not allowed when base register "
5462 "in register list");
5466 case ARM::LDMIA_UPD:
5467 case ARM::LDMDB_UPD:
5468 case ARM::LDMIB_UPD:
5469 case ARM::LDMDA_UPD:
5475 case ARM::t2LDMIA_UPD:
5476 case ARM::t2LDMDB_UPD:
5477 case ARM::t2STMIA_UPD:
5478 case ARM::t2STMDB_UPD: {
5481 "writeback register not allowed in register list");
5484 case ARM::sysLDMIA_UPD:
5485 case ARM::sysLDMDA_UPD:
5486 case ARM::sysLDMDB_UPD:
5487 case ARM::sysLDMIB_UPD:
5489 return Error(Operands[4]->getStartLoc(),
5490 "writeback register only allowed on system LDM "
5491 "if PC in register-list");
5493 case ARM::sysSTMIA_UPD:
5494 case ARM::sysSTMDA_UPD:
5495 case ARM::sysSTMDB_UPD:
5496 case ARM::sysSTMIB_UPD:
5497 return Error(Operands[2]->getStartLoc(),
5498 "system STM cannot have writeback register");
5509 if (Operands.
size() == 6 &&
5510 (((ARMOperand*)Operands[3])->getReg() !=
5511 ((ARMOperand*)Operands[5])->getReg()) &&
5512 (((ARMOperand*)Operands[3])->getReg() !=
5513 ((ARMOperand*)Operands[4])->getReg())) {
5514 return Error(Operands[3]->getStartLoc(),
5515 "destination register must match source register");
5523 bool ListContainsBase;
5526 return Error(Operands[2]->getStartLoc(),
5527 "registers must be in range r0-r7 or pc");
5531 bool ListContainsBase;
5534 return Error(Operands[2]->getStartLoc(),
5535 "registers must be in range r0-r7 or lr");
5538 case ARM::tSTMIA_UPD: {
5539 bool ListContainsBase, InvalidLowList;
5541 0, ListContainsBase);
5542 if (InvalidLowList && !isThumbTwo())
5543 return Error(Operands[4]->getStartLoc(),
5544 "registers must be in range r0-r7");
5548 if (InvalidLowList && ListContainsBase)
5549 return Error(Operands[4]->getStartLoc(),
5550 "writeback operator '!' not allowed when base register "
5551 "in register list");
5554 case ARM::tADDrSP: {
5557 if (!isThumbTwo() &&
5559 return Error(Operands[4]->getStartLoc(),
5560 "source register must be the same as destination");
5566 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5567 return Error(Operands[2]->getStartLoc(),
"branch target out of range");
5570 int op = (Operands[2]->isImm()) ? 2 : 3;
5571 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5572 return Error(Operands[op]->getStartLoc(),
"branch target out of range");
5577 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5578 return Error(Operands[2]->getStartLoc(),
"branch target out of range");
5581 int Op = (Operands[2]->isImm()) ? 2 : 3;
5582 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5583 return Error(Operands[Op]->getStartLoc(),
"branch target out of range");
5595 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VST1LNd8_UPD;
5596 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VST1LNd16_UPD;
5597 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VST1LNd32_UPD;
5598 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1;
return ARM::VST1LNd8_UPD;
5599 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1;
return ARM::VST1LNd16_UPD;
5600 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1;
return ARM::VST1LNd32_UPD;
5601 case ARM::VST1LNdAsm_8: Spacing = 1;
return ARM::VST1LNd8;
5602 case ARM::VST1LNdAsm_16: Spacing = 1;
return ARM::VST1LNd16;
5603 case ARM::VST1LNdAsm_32: Spacing = 1;
return ARM::VST1LNd32;
5606 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VST2LNd8_UPD;
5607 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VST2LNd16_UPD;
5608 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VST2LNd32_UPD;
5609 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2;
return ARM::VST2LNq16_UPD;
5610 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2;
return ARM::VST2LNq32_UPD;
5612 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1;
return ARM::VST2LNd8_UPD;
5613 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1;
return ARM::VST2LNd16_UPD;
5614 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1;
return ARM::VST2LNd32_UPD;
5615 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2;
return ARM::VST2LNq16_UPD;
5616 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2;
return ARM::VST2LNq32_UPD;
5618 case ARM::VST2LNdAsm_8: Spacing = 1;
return ARM::VST2LNd8;
5619 case ARM::VST2LNdAsm_16: Spacing = 1;
return ARM::VST2LNd16;
5620 case ARM::VST2LNdAsm_32: Spacing = 1;
return ARM::VST2LNd32;
5621 case ARM::VST2LNqAsm_16: Spacing = 2;
return ARM::VST2LNq16;
5622 case ARM::VST2LNqAsm_32: Spacing = 2;
return ARM::VST2LNq32;
5625 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VST3LNd8_UPD;
5626 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VST3LNd16_UPD;
5627 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VST3LNd32_UPD;
5628 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1;
return ARM::VST3LNq16_UPD;
5629 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2;
return ARM::VST3LNq32_UPD;
5630 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1;
return ARM::VST3LNd8_UPD;
5631 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1;
return ARM::VST3LNd16_UPD;
5632 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1;
return ARM::VST3LNd32_UPD;
5633 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2;
return ARM::VST3LNq16_UPD;
5634 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2;
return ARM::VST3LNq32_UPD;
5635 case ARM::VST3LNdAsm_8: Spacing = 1;
return ARM::VST3LNd8;
5636 case ARM::VST3LNdAsm_16: Spacing = 1;
return ARM::VST3LNd16;
5637 case ARM::VST3LNdAsm_32: Spacing = 1;
return ARM::VST3LNd32;
5638 case ARM::VST3LNqAsm_16: Spacing = 2;
return ARM::VST3LNq16;
5639 case ARM::VST3LNqAsm_32: Spacing = 2;
return ARM::VST3LNq32;
5642 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1;
return ARM::VST3d8_UPD;
5643 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1;
return ARM::VST3d16_UPD;
5644 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1;
return ARM::VST3d32_UPD;
5645 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2;
return ARM::VST3q8_UPD;
5646 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2;
return ARM::VST3q16_UPD;
5647 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2;
return ARM::VST3q32_UPD;
5648 case ARM::VST3dWB_register_Asm_8: Spacing = 1;
return ARM::VST3d8_UPD;
5649 case ARM::VST3dWB_register_Asm_16: Spacing = 1;
return ARM::VST3d16_UPD;
5650 case ARM::VST3dWB_register_Asm_32: Spacing = 1;
return ARM::VST3d32_UPD;
5651 case ARM::VST3qWB_register_Asm_8: Spacing = 2;
return ARM::VST3q8_UPD;
5652 case ARM::VST3qWB_register_Asm_16: Spacing = 2;
return ARM::VST3q16_UPD;
5653 case ARM::VST3qWB_register_Asm_32: Spacing = 2;
return ARM::VST3q32_UPD;
5654 case ARM::VST3dAsm_8: Spacing = 1;
return ARM::VST3d8;
5655 case ARM::VST3dAsm_16: Spacing = 1;
return ARM::VST3d16;
5656 case ARM::VST3dAsm_32: Spacing = 1;
return ARM::VST3d32;
5657 case ARM::VST3qAsm_8: Spacing = 2;
return ARM::VST3q8;
5658 case ARM::VST3qAsm_16: Spacing = 2;
return ARM::VST3q16;
5659 case ARM::VST3qAsm_32: Spacing = 2;
return ARM::VST3q32;
5662 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VST4LNd8_UPD;
5663 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VST4LNd16_UPD;
5664 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VST4LNd32_UPD;
5665 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1;
return ARM::VST4LNq16_UPD;
5666 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2;
return ARM::VST4LNq32_UPD;
5667 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1;
return ARM::VST4LNd8_UPD;
5668 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1;
return ARM::VST4LNd16_UPD;
5669 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1;
return ARM::VST4LNd32_UPD;
5670 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2;
return ARM::VST4LNq16_UPD;
5671 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2;
return ARM::VST4LNq32_UPD;
5672 case ARM::VST4LNdAsm_8: Spacing = 1;
return ARM::VST4LNd8;
5673 case ARM::VST4LNdAsm_16: Spacing = 1;
return ARM::VST4LNd16;
5674 case ARM::VST4LNdAsm_32: Spacing = 1;
return ARM::VST4LNd32;
5675 case ARM::VST4LNqAsm_16: Spacing = 2;
return ARM::VST4LNq16;
5676 case ARM::VST4LNqAsm_32: Spacing = 2;
return ARM::VST4LNq32;
5679 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1;
return ARM::VST4d8_UPD;
5680 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1;
return ARM::VST4d16_UPD;
5681 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1;
return ARM::VST4d32_UPD;
5682 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2;
return ARM::VST4q8_UPD;
5683 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2;
return ARM::VST4q16_UPD;
5684 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2;
return ARM::VST4q32_UPD;
5685 case ARM::VST4dWB_register_Asm_8: Spacing = 1;
return ARM::VST4d8_UPD;
5686 case ARM::VST4dWB_register_Asm_16: Spacing = 1;
return ARM::VST4d16_UPD;
5687 case ARM::VST4dWB_register_Asm_32: Spacing = 1;
return ARM::VST4d32_UPD;
5688 case ARM::VST4qWB_register_Asm_8: Spacing = 2;
return ARM::VST4q8_UPD;
5689 case ARM::VST4qWB_register_Asm_16: Spacing = 2;
return ARM::VST4q16_UPD;
5690 case ARM::VST4qWB_register_Asm_32: Spacing = 2;
return ARM::VST4q32_UPD;
5691 case ARM::VST4dAsm_8: Spacing = 1;
return ARM::VST4d8;
5692 case ARM::VST4dAsm_16: Spacing = 1;
return ARM::VST4d16;
5693 case ARM::VST4dAsm_32: Spacing = 1;
return ARM::VST4d32;
5694 case ARM::VST4qAsm_8: Spacing = 2;
return ARM::VST4q8;
5695 case ARM::VST4qAsm_16: Spacing = 2;
return ARM::VST4q16;
5696 case ARM::VST4qAsm_32: Spacing = 2;
return ARM::VST4q32;
5704 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD1LNd8_UPD;
5705 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD1LNd16_UPD;
5706 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD1LNd32_UPD;
5707 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1;
return ARM::VLD1LNd8_UPD;
5708 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1;
return ARM::VLD1LNd16_UPD;
5709 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1;
return ARM::VLD1LNd32_UPD;
5710 case ARM::VLD1LNdAsm_8: Spacing = 1;
return ARM::VLD1LNd8;
5711 case ARM::VLD1LNdAsm_16: Spacing = 1;
return ARM::VLD1LNd16;
5712 case ARM::VLD1LNdAsm_32: Spacing = 1;
return ARM::VLD1LNd32;
5715 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD2LNd8_UPD;
5716 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD2LNd16_UPD;
5717 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD2LNd32_UPD;
5718 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD2LNq16_UPD;
5719 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2;
return ARM::VLD2LNq32_UPD;
5720 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1;
return ARM::VLD2LNd8_UPD;
5721 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1;
return ARM::VLD2LNd16_UPD;
5722 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1;
return ARM::VLD2LNd32_UPD;
5723 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2;
return ARM::VLD2LNq16_UPD;
5724 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2;
return ARM::VLD2LNq32_UPD;
5725 case ARM::VLD2LNdAsm_8: Spacing = 1;
return ARM::VLD2LNd8;
5726 case ARM::VLD2LNdAsm_16: Spacing = 1;
return ARM::VLD2LNd16;
5727 case ARM::VLD2LNdAsm_32: Spacing = 1;
return ARM::VLD2LNd32;
5728 case ARM::VLD2LNqAsm_16: Spacing = 2;
return ARM::VLD2LNq16;
5729 case ARM::VLD2LNqAsm_32: Spacing = 2;
return ARM::VLD2LNq32;
5732 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD3DUPd8_UPD;
5733 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD3DUPd16_UPD;
5734 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD3DUPd32_UPD;
5735 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD3DUPq8_UPD;
5736 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD3DUPq16_UPD;
5737 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2;
return ARM::VLD3DUPq32_UPD;
5738 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1;
return ARM::VLD3DUPd8_UPD;
5739 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1;
return ARM::VLD3DUPd16_UPD;
5740 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1;
return ARM::VLD3DUPd32_UPD;
5741 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2;
return ARM::VLD3DUPq8_UPD;
5742 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2;
return ARM::VLD3DUPq16_UPD;
5743 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2;
return ARM::VLD3DUPq32_UPD;
5744 case ARM::VLD3DUPdAsm_8: Spacing = 1;
return ARM::VLD3DUPd8;
5745 case ARM::VLD3DUPdAsm_16: Spacing = 1;
return ARM::VLD3DUPd16;
5746 case ARM::VLD3DUPdAsm_32: Spacing = 1;
return ARM::VLD3DUPd32;
5747 case ARM::VLD3DUPqAsm_8: Spacing = 2;
return ARM::VLD3DUPq8;
5748 case ARM::VLD3DUPqAsm_16: Spacing = 2;
return ARM::VLD3DUPq16;
5749 case ARM::VLD3DUPqAsm_32: Spacing = 2;
return ARM::VLD3DUPq32;
5752 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD3LNd8_UPD;
5753 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD3LNd16_UPD;
5754 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD3LNd32_UPD;
5755 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD3LNq16_UPD;
5756 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2;
return ARM::VLD3LNq32_UPD;
5757 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1;
return ARM::VLD3LNd8_UPD;
5758 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1;
return ARM::VLD3LNd16_UPD;
5759 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1;
return ARM::VLD3LNd32_UPD;
5760 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2;
return ARM::VLD3LNq16_UPD;
5761 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2;
return ARM::VLD3LNq32_UPD;
5762 case ARM::VLD3LNdAsm_8: Spacing = 1;
return ARM::VLD3LNd8;
5763 case ARM::VLD3LNdAsm_16: Spacing = 1;
return ARM::VLD3LNd16;
5764 case ARM::VLD3LNdAsm_32: Spacing = 1;
return ARM::VLD3LNd32;
5765 case ARM::VLD3LNqAsm_16: Spacing = 2;
return ARM::VLD3LNq16;
5766 case ARM::VLD3LNqAsm_32: Spacing = 2;
return ARM::VLD3LNq32;
5769 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD3d8_UPD;
5770 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD3d16_UPD;
5771 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD3d32_UPD;
5772 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2;
return ARM::VLD3q8_UPD;
5773 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2;
return ARM::VLD3q16_UPD;
5774 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2;
return ARM::VLD3q32_UPD;
5775 case ARM::VLD3dWB_register_Asm_8: Spacing = 1;
return ARM::VLD3d8_UPD;
5776 case ARM::VLD3dWB_register_Asm_16: Spacing = 1;
return ARM::VLD3d16_UPD;
5777 case ARM::VLD3dWB_register_Asm_32: Spacing = 1;
return ARM::VLD3d32_UPD;
5778 case ARM::VLD3qWB_register_Asm_8: Spacing = 2;
return ARM::VLD3q8_UPD;
5779 case ARM::VLD3qWB_register_Asm_16: Spacing = 2;
return ARM::VLD3q16_UPD;
5780 case ARM::VLD3qWB_register_Asm_32: Spacing = 2;
return ARM::VLD3q32_UPD;
5781 case ARM::VLD3dAsm_8: Spacing = 1;
return ARM::VLD3d8;
5782 case ARM::VLD3dAsm_16: Spacing = 1;
return ARM::VLD3d16;
5783 case ARM::VLD3dAsm_32: Spacing = 1;
return ARM::VLD3d32;
5784 case ARM::VLD3qAsm_8: Spacing = 2;
return ARM::VLD3q8;
5785 case ARM::VLD3qAsm_16: Spacing = 2;
return ARM::VLD3q16;
5786 case ARM::VLD3qAsm_32: Spacing = 2;
return ARM::VLD3q32;
5789 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD4LNd8_UPD;
5790 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD4LNd16_UPD;
5791 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD4LNd32_UPD;
5792 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD4LNq16_UPD;
5793 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2;
return ARM::VLD4LNq32_UPD;
5794 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1;
return ARM::VLD4LNd8_UPD;
5795 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1;
return ARM::VLD4LNd16_UPD;
5796 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1;
return ARM::VLD4LNd32_UPD;
5797 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2;
return ARM::VLD4LNq16_UPD;
5798 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2;
return ARM::VLD4LNq32_UPD;
5799 case ARM::VLD4LNdAsm_8: Spacing = 1;
return ARM::VLD4LNd8;
5800 case ARM::VLD4LNdAsm_16: Spacing = 1;
return ARM::VLD4LNd16;
5801 case ARM::VLD4LNdAsm_32: Spacing = 1;
return ARM::VLD4LNd32;
5802 case ARM::VLD4LNqAsm_16: Spacing = 2;
return ARM::VLD4LNq16;
5803 case ARM::VLD4LNqAsm_32: Spacing = 2;
return ARM::VLD4LNq32;
5806 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD4DUPd8_UPD;
5807 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD4DUPd16_UPD;
5808 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD4DUPd32_UPD;
5809 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD4DUPq8_UPD;
5810 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD4DUPq16_UPD;
5811 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2;
return ARM::VLD4DUPq32_UPD;
5812 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1;
return ARM::VLD4DUPd8_UPD;
5813 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1;
return ARM::VLD4DUPd16_UPD;
5814 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1;
return ARM::VLD4DUPd32_UPD;
5815 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2;
return ARM::VLD4DUPq8_UPD;
5816 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2;
return ARM::VLD4DUPq16_UPD;
5817 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2;
return ARM::VLD4DUPq32_UPD;
5818 case ARM::VLD4DUPdAsm_8: Spacing = 1;
return ARM::VLD4DUPd8;
5819 case ARM::VLD4DUPdAsm_16: Spacing = 1;
return ARM::VLD4DUPd16;
5820 case ARM::VLD4DUPdAsm_32: Spacing = 1;
return ARM::VLD4DUPd32;
5821 case ARM::VLD4DUPqAsm_8: Spacing = 2;
return ARM::VLD4DUPq8;
5822 case ARM::VLD4DUPqAsm_16: Spacing = 2;
return ARM::VLD4DUPq16;
5823 case ARM::VLD4DUPqAsm_32: Spacing = 2;
return ARM::VLD4DUPq32;
5826 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1;
return ARM::VLD4d8_UPD;
5827 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1;
return ARM::VLD4d16_UPD;
5828 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1;
return ARM::VLD4d32_UPD;
5829 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2;
return ARM::VLD4q8_UPD;
5830 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2;
return ARM::VLD4q16_UPD;
5831 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2;
return ARM::VLD4q32_UPD;
5832 case ARM::VLD4dWB_register_Asm_8: Spacing = 1;
return ARM::VLD4d8_UPD;
5833 case ARM::VLD4dWB_register_Asm_16: Spacing = 1;
return ARM::VLD4d16_UPD;
5834 case ARM::VLD4dWB_register_Asm_32: Spacing = 1;
return ARM::VLD4d32_UPD;
5835 case ARM::VLD4qWB_register_Asm_8: Spacing = 2;
return ARM::VLD4q8_UPD;
5836 case ARM::VLD4qWB_register_Asm_16: Spacing = 2;
return ARM::VLD4q16_UPD;
5837 case ARM::VLD4qWB_register_Asm_32: Spacing = 2;
return ARM::VLD4q32_UPD;
5838 case ARM::VLD4dAsm_8: Spacing = 1;
return ARM::VLD4d8;
5839 case ARM::VLD4dAsm_16: Spacing = 1;
return ARM::VLD4d16;
5840 case ARM::VLD4dAsm_32: Spacing = 1;
return ARM::VLD4d32;
5841 case ARM::VLD4qAsm_8: Spacing = 2;
return ARM::VLD4q8;
5842 case ARM::VLD4qAsm_16: Spacing = 2;
return ARM::VLD4q16;
5843 case ARM::VLD4qAsm_32: Spacing = 2;
return ARM::VLD4q32;
5848 processInstruction(
MCInst &Inst,
5866 case ARM::t2LDRpcrel:
5870 !(
static_cast<ARMOperand*
>(Operands[2])->isToken() &&
5871 static_cast<ARMOperand*
>(Operands[2])->
getToken() ==
".w"))
5876 case ARM::t2LDRBpcrel:
5879 case ARM::t2LDRHpcrel:
5882 case ARM::t2LDRSBpcrel:
5885 case ARM::t2LDRSHpcrel:
5889 case ARM::VST1LNdWB_register_Asm_8:
5890 case ARM::VST1LNdWB_register_Asm_16:
5891 case ARM::VST1LNdWB_register_Asm_32: {
5909 case ARM::VST2LNdWB_register_Asm_8:
5910 case ARM::VST2LNdWB_register_Asm_16:
5911 case ARM::VST2LNdWB_register_Asm_32:
5912 case ARM::VST2LNqWB_register_Asm_16:
5913 case ARM::VST2LNqWB_register_Asm_32: {
5933 case ARM::VST3LNdWB_register_Asm_8:
5934 case ARM::VST3LNdWB_register_Asm_16:
5935 case ARM::VST3LNdWB_register_Asm_32:
5936 case ARM::VST3LNqWB_register_Asm_16:
5937 case ARM::VST3LNqWB_register_Asm_32: {
5959 case ARM::VST4LNdWB_register_Asm_8:
5960 case ARM::VST4LNdWB_register_Asm_16:
5961 case ARM::VST4LNdWB_register_Asm_32:
5962 case ARM::VST4LNqWB_register_Asm_16:
5963 case ARM::VST4LNqWB_register_Asm_32: {
5987 case ARM::VST1LNdWB_fixed_Asm_8:
5988 case ARM::VST1LNdWB_fixed_Asm_16:
5989 case ARM::VST1LNdWB_fixed_Asm_32: {
6007 case ARM::VST2LNdWB_fixed_Asm_8:
6008 case ARM::VST2LNdWB_fixed_Asm_16:
6009 case ARM::VST2LNdWB_fixed_Asm_32:
6010 case ARM::VST2LNqWB_fixed_Asm_16:
6011 case ARM::VST2LNqWB_fixed_Asm_32: {
6031 case ARM::VST3LNdWB_fixed_Asm_8:
6032 case ARM::VST3LNdWB_fixed_Asm_16:
6033 case ARM::VST3LNdWB_fixed_Asm_32:
6034 case ARM::VST3LNqWB_fixed_Asm_16:
6035 case ARM::VST3LNqWB_fixed_Asm_32: {
6057 case ARM::VST4LNdWB_fixed_Asm_8:
6058 case ARM::VST4LNdWB_fixed_Asm_16:
6059 case ARM::VST4LNdWB_fixed_Asm_32:
6060 case ARM::VST4LNqWB_fixed_Asm_16:
6061 case ARM::VST4LNqWB_fixed_Asm_32: {
6085 case ARM::VST1LNdAsm_8:
6086 case ARM::VST1LNdAsm_16:
6087 case ARM::VST1LNdAsm_32: {
6103 case ARM::VST2LNdAsm_8:
6104 case ARM::VST2LNdAsm_16:
6105 case ARM::VST2LNdAsm_32:
6106 case ARM::VST2LNqAsm_16:
6107 case ARM::VST2LNqAsm_32: {
6125 case ARM::VST3LNdAsm_8:
6126 case ARM::VST3LNdAsm_16:
6127 case ARM::VST3LNdAsm_32:
6128 case ARM::VST3LNqAsm_16:
6129 case ARM::VST3LNqAsm_32: {
6149 case ARM::VST4LNdAsm_8:
6150 case ARM::VST4LNdAsm_16:
6151 case ARM::VST4LNdAsm_32:
6152 case ARM::VST4LNqAsm_16:
6153 case ARM::VST4LNqAsm_32: {
6176 case ARM::VLD1LNdWB_register_Asm_8:
6177 case ARM::VLD1LNdWB_register_Asm_16:
6178 case ARM::VLD1LNdWB_register_Asm_32: {
6197 case ARM::VLD2LNdWB_register_Asm_8:
6198 case ARM::VLD2LNdWB_register_Asm_16:
6199 case ARM::VLD2LNdWB_register_Asm_32:
6200 case ARM::VLD2LNqWB_register_Asm_16:
6201 case ARM::VLD2LNqWB_register_Asm_32: {
6224 case ARM::VLD3LNdWB_register_Asm_8:
6225 case ARM::VLD3LNdWB_register_Asm_16:
6226 case ARM::VLD3LNdWB_register_Asm_32:
6227 case ARM::VLD3LNqWB_register_Asm_16:
6228 case ARM::VLD3LNqWB_register_Asm_32: {
6255 case ARM::VLD4LNdWB_register_Asm_8:
6256 case ARM::VLD4LNdWB_register_Asm_16:
6257 case ARM::VLD4LNdWB_register_Asm_32:
6258 case ARM::VLD4LNqWB_register_Asm_16:
6259 case ARM::VLD4LNqWB_register_Asm_32: {
6290 case ARM::VLD1LNdWB_fixed_Asm_8:
6291 case ARM::VLD1LNdWB_fixed_Asm_16:
6292 case ARM::VLD1LNdWB_fixed_Asm_32: {
6311 case ARM::VLD2LNdWB_fixed_Asm_8:
6312 case ARM::VLD2LNdWB_fixed_Asm_16:
6313 case ARM::VLD2LNdWB_fixed_Asm_32:
6314 case ARM::VLD2LNqWB_fixed_Asm_16:
6315 case ARM::VLD2LNqWB_fixed_Asm_32: {
6338 case ARM::VLD3LNdWB_fixed_Asm_8:
6339 case ARM::VLD3LNdWB_fixed_Asm_16:
6340 case ARM::VLD3LNdWB_fixed_Asm_32:
6341 case ARM::VLD3LNqWB_fixed_Asm_16:
6342 case ARM::VLD3LNqWB_fixed_Asm_32: {
6369 case ARM::VLD4LNdWB_fixed_Asm_8:
6370 case ARM::VLD4LNdWB_fixed_Asm_16:
6371 case ARM::VLD4LNdWB_fixed_Asm_32:
6372 case ARM::VLD4LNqWB_fixed_Asm_16:
6373 case ARM::VLD4LNqWB_fixed_Asm_32: {
6404 case ARM::VLD1LNdAsm_8:
6405 case ARM::VLD1LNdAsm_16:
6406 case ARM::VLD1LNdAsm_32: {
6423 case ARM::VLD2LNdAsm_8:
6424 case ARM::VLD2LNdAsm_16:
6425 case ARM::VLD2LNdAsm_32:
6426 case ARM::VLD2LNqAsm_16:
6427 case ARM::VLD2LNqAsm_32: {
6448 case ARM::VLD3LNdAsm_8:
6449 case ARM::VLD3LNdAsm_16:
6450 case ARM::VLD3LNdAsm_32:
6451 case ARM::VLD3LNqAsm_16:
6452 case ARM::VLD3LNqAsm_32: {
6477 case ARM::VLD4LNdAsm_8:
6478 case ARM::VLD4LNdAsm_16:
6479 case ARM::VLD4LNdAsm_32:
6480 case ARM::VLD4LNqAsm_16:
6481 case ARM::VLD4LNqAsm_32: {
6511 case ARM::VLD3DUPdAsm_8:
6512 case ARM::VLD3DUPdAsm_16:
6513 case ARM::VLD3DUPdAsm_32:
6514 case ARM::VLD3DUPqAsm_8:
6515 case ARM::VLD3DUPqAsm_16:
6516 case ARM::VLD3DUPqAsm_32: {
6533 case ARM::VLD3DUPdWB_fixed_Asm_8:
6534 case ARM::VLD3DUPdWB_fixed_Asm_16:
6535 case ARM::VLD3DUPdWB_fixed_Asm_32:
6536 case ARM::VLD3DUPqWB_fixed_Asm_8:
6537 case ARM::VLD3DUPqWB_fixed_Asm_16:
6538 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6557 case ARM::VLD3DUPdWB_register_Asm_8:
6558 case ARM::VLD3DUPdWB_register_Asm_16:
6559 case ARM::VLD3DUPdWB_register_Asm_32:
6560 case ARM::VLD3DUPqWB_register_Asm_8:
6561 case ARM::VLD3DUPqWB_register_Asm_16:
6562 case ARM::VLD3DUPqWB_register_Asm_32: {
6582 case ARM::VLD3dAsm_8:
6583 case ARM::VLD3dAsm_16:
6584 case ARM::VLD3dAsm_32:
6585 case ARM::VLD3qAsm_8:
6586 case ARM::VLD3qAsm_16:
6587 case ARM::VLD3qAsm_32: {
6604 case ARM::VLD3dWB_fixed_Asm_8:
6605 case ARM::VLD3dWB_fixed_Asm_16:
6606 case ARM::VLD3dWB_fixed_Asm_32:
6607 case ARM::VLD3qWB_fixed_Asm_8:
6608 case ARM::VLD3qWB_fixed_Asm_16:
6609 case ARM::VLD3qWB_fixed_Asm_32: {
6628 case ARM::VLD3dWB_register_Asm_8:
6629 case ARM::VLD3dWB_register_Asm_16:
6630 case ARM::VLD3dWB_register_Asm_32:
6631 case ARM::VLD3qWB_register_Asm_8:
6632 case ARM::VLD3qWB_register_Asm_16:
6633 case ARM::VLD3qWB_register_Asm_32: {
6653 case ARM::VLD4DUPdAsm_8:
6654 case ARM::VLD4DUPdAsm_16:
6655 case ARM::VLD4DUPdAsm_32:
6656 case ARM::VLD4DUPqAsm_8:
6657 case ARM::VLD4DUPqAsm_16:
6658 case ARM::VLD4DUPqAsm_32: {
6677 case ARM::VLD4DUPdWB_fixed_Asm_8:
6678 case ARM::VLD4DUPdWB_fixed_Asm_16:
6679 case ARM::VLD4DUPdWB_fixed_Asm_32:
6680 case ARM::VLD4DUPqWB_fixed_Asm_8:
6681 case ARM::VLD4DUPqWB_fixed_Asm_16:
6682 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6703 case ARM::VLD4DUPdWB_register_Asm_8:
6704 case ARM::VLD4DUPdWB_register_Asm_16:
6705 case ARM::VLD4DUPdWB_register_Asm_32:
6706 case ARM::VLD4DUPqWB_register_Asm_8:
6707 case ARM::VLD4DUPqWB_register_Asm_16:
6708 case ARM::VLD4DUPqWB_register_Asm_32: {
6730 case ARM::VLD4dAsm_8:
6731 case ARM::VLD4dAsm_16:
6732 case ARM::VLD4dAsm_32:
6733 case ARM::VLD4qAsm_8:
6734 case ARM::VLD4qAsm_16:
6735 case ARM::VLD4qAsm_32: {
6754 case ARM::VLD4dWB_fixed_Asm_8:
6755 case ARM::VLD4dWB_fixed_Asm_16:
6756 case ARM::VLD4dWB_fixed_Asm_32:
6757 case ARM::VLD4qWB_fixed_Asm_8:
6758 case ARM::VLD4qWB_fixed_Asm_16:
6759 case ARM::VLD4qWB_fixed_Asm_32: {
6780 case ARM::VLD4dWB_register_Asm_8:
6781 case ARM::VLD4dWB_register_Asm_16:
6782 case ARM::VLD4dWB_register_Asm_32:
6783 case ARM::VLD4qWB_register_Asm_8:
6784 case ARM::VLD4qWB_register_Asm_16:
6785 case ARM::VLD4qWB_register_Asm_32: {
6807 case ARM::VST3dAsm_8:
6808 case ARM::VST3dAsm_16:
6809 case ARM::VST3dAsm_32:
6810 case ARM::VST3qAsm_8:
6811 case ARM::VST3qAsm_16:
6812 case ARM::VST3qAsm_32: {
6829 case ARM::VST3dWB_fixed_Asm_8:
6830 case ARM::VST3dWB_fixed_Asm_16:
6831 case ARM::VST3dWB_fixed_Asm_32:
6832 case ARM::VST3qWB_fixed_Asm_8:
6833 case ARM::VST3qWB_fixed_Asm_16:
6834 case ARM::VST3qWB_fixed_Asm_32: {
6853 case ARM::VST3dWB_register_Asm_8:
6854 case ARM::VST3dWB_register_Asm_16:
6855 case ARM::VST3dWB_register_Asm_32:
6856 case ARM::VST3qWB_register_Asm_8:
6857 case ARM::VST3qWB_register_Asm_16:
6858 case ARM::VST3qWB_register_Asm_32: {
6878 case ARM::VST4dAsm_8:
6879 case ARM::VST4dAsm_16:
6880 case ARM::VST4dAsm_32:
6881 case ARM::VST4qAsm_8:
6882 case ARM::VST4qAsm_16:
6883 case ARM::VST4qAsm_32: {
6902 case ARM::VST4dWB_fixed_Asm_8:
6903 case ARM::VST4dWB_fixed_Asm_16:
6904 case ARM::VST4dWB_fixed_Asm_32:
6905 case ARM::VST4qWB_fixed_Asm_8:
6906 case ARM::VST4qWB_fixed_Asm_16:
6907 case ARM::VST4qWB_fixed_Asm_32: {
6928 case ARM::VST4dWB_register_Asm_8:
6929 case ARM::VST4dWB_register_Asm_16:
6930 case ARM::VST4dWB_register_Asm_32:
6931 case ARM::VST4qWB_register_Asm_8:
6932 case ARM::VST4qWB_register_Asm_16:
6933 case ARM::VST4qWB_register_Asm_32: {
6957 case ARM::t2ASRri: {
6961 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6962 static_cast<ARMOperand*
>(Operands[3])->
getToken() ==
".w")) {
6966 case ARM::t2LSLri: NewOpc = ARM::tLSLri;
break;
6967 case ARM::t2LSRri: NewOpc = ARM::tLSRri;
break;
6968 case ARM::t2ASRri: NewOpc = ARM::tASRri;
break;
6987 case ARM::t2MOVSsr: {
6991 bool isNarrow =
false;
6996 inITBlock() == (Inst.
getOpcode() == ARM::t2MOVsr))
7002 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr;
break;
7003 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr;
break;
7004 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr;
break;
7005 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr;
break;
7011 Inst.
getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7018 Inst.
getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7023 case ARM::t2MOVSsi: {
7027 bool isNarrow =
false;
7030 inITBlock() == (Inst.
getOpcode() == ARM::t2MOVsi))
7036 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri;
break;
7037 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri;
break;
7038 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri;
break;
7039 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow =
false;
break;
7040 case ARM_AM::rrx: isNarrow =
false; newOpc = ARM::t2RRX;
break;
7043 if (Amount == 32) Amount = 0;
7048 Inst.
getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7050 if (newOpc != ARM::t2RRX)
7056 Inst.
getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7100 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7109 if (Opc == ARM::MOVsi)
7130 case ARM::t2LDMIA_UPD: {
7146 case ARM::t2STMDB_UPD: {
7162 case ARM::LDMIA_UPD:
7165 if (static_cast<ARMOperand*>(Operands[0])->getToken() ==
"pop" &&
7180 case ARM::STMDB_UPD:
7183 if (static_cast<ARMOperand*>(Operands[0])->getToken() ==
"push" &&
7196 case ARM::t2ADDri12:
7199 if (static_cast<ARMOperand*>(Operands[0])->getToken() !=
"add" ||
7205 case ARM::t2SUBri12:
7208 if (static_cast<ARMOperand*>(Operands[0])->
getToken() !=
"sub" ||
7235 case ARM::t2SUBri: {
7242 (
unsigned)Inst.getOperand(2).getImm() > 255 ||
7243 ((!inITBlock() && Inst.getOperand(5).
getReg() !=
ARM::CPSR) ||
7244 (inITBlock() && Inst.getOperand(5).
getReg() != 0)) ||
7245 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7246 static_cast<ARMOperand*>(Operands[3])->
getToken() == ".w"))
7249 TmpInst.setOpcode(Inst.getOpcode() ==
ARM::t2ADDri ?
7250 ARM::tADDi8 :
ARM::tSUBi8);
7251 TmpInst.addOperand(Inst.getOperand(0));
7252 TmpInst.addOperand(Inst.getOperand(5));
7253 TmpInst.addOperand(Inst.getOperand(0));
7254 TmpInst.addOperand(Inst.getOperand(2));
7255 TmpInst.addOperand(Inst.getOperand(3));
7256 TmpInst.addOperand(Inst.getOperand(4));
7260 case
ARM::t2ADDrr: {
7267 (
static_cast<ARMOperand*
>(Operands[3])->isToken() &&
7268 static_cast<ARMOperand*
>(Operands[3])->
getToken() ==
".w"))
7280 case ARM::tADDrSP: {
7324 bool hasWritebackToken =
7325 (
static_cast<ARMOperand*
>(Operands[3])->isToken() &&
7326 static_cast<ARMOperand*
>(Operands[3])->
getToken() ==
"!");
7327 bool listContainsBase;
7329 (!listContainsBase && !hasWritebackToken) ||
7330 (listContainsBase && hasWritebackToken)) {
7332 assert (isThumbTwo());
7333 Inst.
setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7336 if (hasWritebackToken)
7343 case ARM::tSTMIA_UPD: {
7348 bool listContainsBase;
7351 assert (isThumbTwo());
7358 bool listContainsBase;
7364 assert (isThumbTwo());
7372 bool listContainsBase;
7375 assert (isThumbTwo());
7390 (!
static_cast<ARMOperand*
>(Operands[2])->isToken() ||
7391 static_cast<ARMOperand*
>(Operands[2])->
getToken() !=
".w")) {
7412 (!
static_cast<ARMOperand*
>(Operands[2])->isToken() ||
7413 static_cast<ARMOperand*
>(Operands[2])->
getToken() !=
".w")) {
7435 (!
static_cast<ARMOperand*
>(Operands[2])->isToken() ||
7436 static_cast<ARMOperand*
>(Operands[2])->
getToken() !=
".w")) {
7440 case ARM::t2SXTH: NewOpc = ARM::tSXTH;
break;
7441 case ARM::t2SXTB: NewOpc = ARM::tSXTB;
break;
7442 case ARM::t2UXTH: NewOpc = ARM::tUXTH;
break;
7443 case ARM::t2UXTB: NewOpc = ARM::tUXTB;
break;
7487 case ARM::ANDrsi: newOpc = ARM::ANDrr;
break;
7488 case ARM::ORRrsi: newOpc = ARM::ORRrr;
break;
7489 case ARM::EORrsi: newOpc = ARM::EORrr;
break;
7490 case ARM::BICrsi: newOpc = ARM::BICrr;
break;
7491 case ARM::SUBrsi: newOpc = ARM::SUBrr;
break;
7492 case ARM::ADDrsi: newOpc = ARM::ADDrr;
break;
7518 unsigned Mask = MO.
getImm();
7519 unsigned OrigMask = Mask;
7522 assert(Mask && TZ <= 3 &&
"illegal IT mask value!");
7523 Mask ^= (0xE << TZ) & 0xF;
7529 assert(!inITBlock() &&
"nested IT blocks?!");
7531 ITState.Mask = OrigMask;
7532 ITState.CurPosition = 0;
7533 ITState.FirstCond =
true;
7549 (!
static_cast<ARMOperand*
>(Operands[3])->isToken() ||
7550 !
static_cast<ARMOperand*
>(Operands[3])->
getToken().equals_lower(
".w"))) {
7554 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr;
break;
7555 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr;
break;
7556 case ARM::t2ASRrr: NewOpc = ARM::tASRrr;
break;
7557 case ARM::t2SBCrr: NewOpc = ARM::tSBC;
break;
7558 case ARM::t2RORrr: NewOpc = ARM::tROR;
break;
7559 case ARM::t2BICrr: NewOpc = ARM::tBIC;
break;
7588 (!
static_cast<ARMOperand*
>(Operands[3])->isToken() ||
7589 !
static_cast<ARMOperand*
>(Operands[3])->
getToken().equals_lower(
".w"))) {
7593 case ARM::t2ADCrr: NewOpc = ARM::tADC;
break;
7594 case ARM::t2ANDrr: NewOpc = ARM::tAND;
break;
7595 case ARM::t2EORrr: NewOpc = ARM::tEOR;
break;
7596 case ARM::t2ORRrr: NewOpc = ARM::tORR;
break;
7620 unsigned ARMAsmParser::checkTargetMatchPredicate(
MCInst &Inst) {
7627 "optionally flag setting instruction missing optional def operand");
7629 "operand count mismatch!");
7638 return Match_MnemonicFail;
7643 return Match_RequiresITBlock;
7646 return Match_RequiresNotITBlock;
7650 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7653 return Match_RequiresThumb2;
7655 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7658 return Match_RequiresV6;
7659 return Match_Success;
7664 MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
7667 bool MatchingInlineAsm) {
7669 unsigned MatchResult;
7671 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7673 switch (MatchResult) {
7678 if (validateInstruction(Inst, Operands)) {
7681 forwardITPosition();
7686 bool wasInITBlock = inITBlock();
7692 while (processInstruction(Inst, Operands))
7696 if (wasInITBlock && hasV8Ops() && isThumb() &&
7698 Warning(IDLoc,
"deprecated instruction in IT block");
7705 forwardITPosition();
7715 case Match_MissingFeature: {
7716 assert(ErrorInfo &&
"Unknown missing feature!");
7719 std::string Msg =
"instruction requires:";
7721 for (
unsigned i = 0; i < (
sizeof(ErrorInfo)*8-1); ++i) {
7722 if (ErrorInfo & Mask) {
7728 return Error(IDLoc, Msg);
7730 case Match_InvalidOperand: {
7731 SMLoc ErrorLoc = IDLoc;
7732 if (ErrorInfo != ~0U) {
7733 if (ErrorInfo >= Operands.
size())
7734 return Error(IDLoc,
"too few operands for instruction");
7736 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7737 if (ErrorLoc ==
SMLoc()) ErrorLoc = IDLoc;
7740 return Error(ErrorLoc,
"invalid operand for instruction");
7742 case Match_MnemonicFail:
7743 return Error(IDLoc,
"invalid instruction",
7744 ((ARMOperand*)Operands[0])->getLocRange());
7745 case Match_RequiresNotITBlock:
7746 return Error(IDLoc,
"flag setting instruction only valid outside IT block");
7747 case Match_RequiresITBlock:
7748 return Error(IDLoc,
"instruction only valid inside IT block");
7749 case Match_RequiresV6:
7750 return Error(IDLoc,
"instruction variant requires ARMv6 or later");
7751 case Match_RequiresThumb2:
7752 return Error(IDLoc,
"instruction variant requires Thumb2");
7753 case Match_ImmRange0_15: {
7754 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7755 if (ErrorLoc ==
SMLoc()) ErrorLoc = IDLoc;
7756 return Error(ErrorLoc,
"immediate operand must be in the range [0,15]");
7758 case Match_ImmRange0_239: {
7759 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7760 if (ErrorLoc ==
SMLoc()) ErrorLoc = IDLoc;
7761 return Error(ErrorLoc,
"immediate operand must be in the range [0,239]");
7769 bool ARMAsmParser::ParseDirective(
AsmToken DirectiveID) {
7771 if (IDVal ==
".word")
7772 return parseDirectiveWord(4, DirectiveID.
getLoc());
7773 else if (IDVal ==
".thumb")
7774 return parseDirectiveThumb(DirectiveID.
getLoc());
7775 else if (IDVal ==
".arm")
7776 return parseDirectiveARM(DirectiveID.
getLoc());
7777 else if (IDVal ==
".thumb_func")
7778 return parseDirectiveThumbFunc(DirectiveID.
getLoc());
7779 else if (IDVal ==
".code")
7780 return parseDirectiveCode(DirectiveID.
getLoc());
7781 else if (IDVal ==
".syntax")
7782 return parseDirectiveSyntax(DirectiveID.
getLoc());
7783 else if (IDVal ==
".unreq")
7784 return parseDirectiveUnreq(DirectiveID.
getLoc());
7785 else if (IDVal ==
".arch")
7786 return parseDirectiveArch(DirectiveID.
getLoc());
7787 else if (IDVal ==
".eabi_attribute")
7788 return parseDirectiveEabiAttr(DirectiveID.
getLoc());
7789 else if (IDVal ==
".cpu")
7790 return parseDirectiveCPU(DirectiveID.
getLoc());
7791 else if (IDVal ==
".fpu")
7792 return parseDirectiveFPU(DirectiveID.
getLoc());
7793 else if (IDVal ==
".fnstart")
7794 return parseDirectiveFnStart(DirectiveID.
getLoc());
7795 else if (IDVal ==
".fnend")
7796 return parseDirectiveFnEnd(DirectiveID.
getLoc());
7797 else if (IDVal ==
".cantunwind")
7798 return parseDirectiveCantUnwind(DirectiveID.
getLoc());
7799 else if (IDVal ==
".personality")
7800 return parseDirectivePersonality(DirectiveID.
getLoc());
7801 else if (IDVal ==
".handlerdata")
7802 return parseDirectiveHandlerData(DirectiveID.
getLoc());
7803 else if (IDVal ==
".setfp")
7804 return parseDirectiveSetFP(DirectiveID.
getLoc());
7805 else if (IDVal ==
".pad")
7806 return parseDirectivePad(DirectiveID.
getLoc());
7807 else if (IDVal ==
".save")
7808 return parseDirectiveRegSave(DirectiveID.
getLoc(),
false);
7809 else if (IDVal ==
".vsave")
7810 return parseDirectiveRegSave(DirectiveID.
getLoc(),
true);
7816 bool ARMAsmParser::parseDirectiveWord(
unsigned Size,
SMLoc L) {
7820 if (getParser().parseExpression(Value))
7823 getParser().getStreamer().EmitValue(Value, Size);
7830 return Error(L,
"unexpected token in directive");
7841 bool ARMAsmParser::parseDirectiveThumb(
SMLoc L) {
7843 return Error(L,
"unexpected token in directive");
7847 return Error(L,
"target does not support Thumb mode");
7851 getParser().getStreamer().EmitAssemblerFlag(
MCAF_Code16);
7857 bool ARMAsmParser::parseDirectiveARM(
SMLoc L) {
7859 return Error(L,
"unexpected token in directive");
7863 return Error(L,
"target does not support ARM mode");
7867 getParser().getStreamer().EmitAssemblerFlag(
MCAF_Code32);
7872 if (NextSymbolIsThumb) {
7873 getParser().getStreamer().EmitThumbFunc(Symbol);
7874 NextSymbolIsThumb =
false;
7880 bool ARMAsmParser::parseDirectiveThumbFunc(
SMLoc L) {
7881 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7887 const AsmToken &Tok = Parser.getTok();
7890 return Error(L,
"unexpected token in .thumb_func directive");
7892 getParser().getContext().GetOrCreateSymbol(Tok.
getIdentifier());
7893 getParser().getStreamer().EmitThumbFunc(Func);
7900 return Error(L,
"unexpected token in directive");
7902 NextSymbolIsThumb =
true;
7909 bool ARMAsmParser::parseDirectiveSyntax(
SMLoc L) {
7910 const AsmToken &Tok = Parser.getTok();
7912 return Error(L,
"unexpected token in .syntax directive");
7914 if (Mode ==
"unified" || Mode ==
"UNIFIED")
7916 else if (Mode ==
"divided" || Mode ==
"DIVIDED")
7917 return Error(L,
"'.syntax divided' arm asssembly not supported");
7919 return Error(L,
"unrecognized syntax mode in .syntax directive");
7922 return Error(Parser.getTok().getLoc(),
"unexpected token in directive");
7932 bool ARMAsmParser::parseDirectiveCode(
SMLoc L) {
7933 const AsmToken &Tok = Parser.getTok();
7935 return Error(L,
"unexpected token in .code directive");
7936 int64_t Val = Parser.getTok().getIntVal();
7942 return Error(L,
"invalid operand to .code directive");
7945 return Error(Parser.getTok().getLoc(),
"unexpected token in directive");
7950 return Error(L,
"target does not support Thumb mode");
7954 getParser().getStreamer().EmitAssemblerFlag(
MCAF_Code16);
7957 return Error(L,
"target does not support ARM mode");
7961 getParser().getStreamer().EmitAssemblerFlag(
MCAF_Code32);
7972 SMLoc SRegLoc, ERegLoc;
7973 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7974 Parser.eatToEndOfStatement();
7975 return Error(SRegLoc,
"register name expected");
7980 Parser.eatToEndOfStatement();
7981 return Error(Parser.getTok().getLoc(),
7982 "unexpected input in .req directive.");
7987 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() !=
Reg)
7988 return Error(SRegLoc,
"redefinition of '" + Name +
7989 "' does not match original.");
7996 bool ARMAsmParser::parseDirectiveUnreq(
SMLoc L) {
7998 Parser.eatToEndOfStatement();
7999 return Error(L,
"unexpected input in .unreq directive.");
8001 RegisterReqs.erase(Parser.getTok().getIdentifier());
8008 bool ARMAsmParser::parseDirectiveArch(
SMLoc L) {
8014 bool ARMAsmParser::parseDirectiveEabiAttr(
SMLoc L) {
8016 return Error(L,
"integer expected");
8017 int64_t Tag = Parser.getTok().getIntVal();
8021 return Error(L,
"comma expected");
8024 L = Parser.getTok().getLoc();
8026 return Error(L,
"integer expected");
8027 int64_t Value = Parser.getTok().getIntVal();
8030 getTargetStreamer().emitAttribute(Tag, Value);
8036 bool ARMAsmParser::parseDirectiveCPU(
SMLoc L) {
8037 StringRef CPU = getParser().parseStringToEndOfStatement().
trim();
8044 bool ARMAsmParser::parseDirectiveFPU(
SMLoc L) {
8045 StringRef FPU = getParser().parseStringToEndOfStatement().
trim();
8049 #include "ARMFPUName.def"
8053 return Error(L,
"Unknown FPU name");
8055 getTargetStreamer().emitFPU(ID);
8061 bool ARMAsmParser::parseDirectiveFnStart(
SMLoc L) {
8062 if (FnStartLoc.isValid()) {
8063 Error(L,
".fnstart starts before the end of previous one");
8064 Error(FnStartLoc,
"previous .fnstart starts here");
8069 getTargetStreamer().emitFnStart();
8075 bool ARMAsmParser::parseDirectiveFnEnd(
SMLoc L) {
8077 if (!FnStartLoc.isValid())
8078 return Error(L,
".fnstart must precede .fnend directive");
8081 resetUnwindDirectiveParserState();
8082 getTargetStreamer().emitFnEnd();
8088 bool ARMAsmParser::parseDirectiveCantUnwind(
SMLoc L) {
8091 if (!FnStartLoc.isValid())
8092 return Error(L,
".fnstart must precede .cantunwind directive");
8093 if (HandlerDataLoc.isValid()) {
8094 Error(L,
".cantunwind can't be used with .handlerdata directive");
8095 Error(HandlerDataLoc,
".handlerdata was specified here");
8098 if (PersonalityLoc.isValid()) {
8099 Error(L,
".cantunwind can't be used with .personality directive");
8100 Error(PersonalityLoc,
".personality was specified here");
8104 getTargetStreamer().emitCantUnwind();
8110 bool ARMAsmParser::parseDirectivePersonality(
SMLoc L) {
8113 if (!FnStartLoc.isValid())
8114 return Error(L,
".fnstart must precede .personality directive");
8115 if (CantUnwindLoc.isValid()) {
8116 Error(L,
".personality can't be used with .cantunwind directive");
8117 Error(CantUnwindLoc,
".cantunwind was specified here");
8120 if (HandlerDataLoc.isValid()) {
8121 Error(L,
".personality must precede .handlerdata directive");
8122 Error(HandlerDataLoc,
".handlerdata was specified here");
8128 Parser.eatToEndOfStatement();
8129 return Error(L,
"unexpected input in .personality directive.");
8134 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8135 getTargetStreamer().emitPersonality(PR);
8141 bool ARMAsmParser::parseDirectiveHandlerData(
SMLoc L) {
8144 if (!FnStartLoc.isValid())
8145 return Error(L,
".fnstart must precede .personality directive");
8146 if (CantUnwindLoc.isValid()) {
8147 Error(L,
".handlerdata can't be used with .cantunwind directive");
8148 Error(CantUnwindLoc,
".cantunwind was specified here");
8152 getTargetStreamer().emitHandlerData();
8158 bool ARMAsmParser::parseDirectiveSetFP(
SMLoc L) {
8160 if (!FnStartLoc.isValid())
8161 return Error(L,
".fnstart must precede .setfp directive");
8162 if (HandlerDataLoc.isValid())
8163 return Error(L,
".setfp must precede .handlerdata directive");
8166 SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8167 int NewFPReg = tryParseRegister();
8169 return Error(NewFPRegLoc,
"frame pointer register expected");
8173 return Error(Parser.getTok().getLoc(),
"comma expected");
8177 SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8178 int NewSPReg = tryParseRegister();
8180 return Error(NewSPRegLoc,
"stack pointer register expected");
8182 if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8183 return Error(NewSPRegLoc,
8184 "register should be either $sp or the latest fp register");
8196 return Error(Parser.getTok().getLoc(),
"'#' expected");
8200 const MCExpr *OffsetExpr;
8201 SMLoc ExLoc = Parser.getTok().getLoc();
8203 if (getParser().parseExpression(OffsetExpr, EndLoc))
8204 return Error(ExLoc,
"malformed setfp offset");
8207 return Error(ExLoc,
"setfp offset must be an immediate");
8212 getTargetStreamer().emitSetFP(static_cast<unsigned>(NewFPReg),
8213 static_cast<unsigned>(NewSPReg), Offset);
8219 bool ARMAsmParser::parseDirectivePad(
SMLoc L) {
8221 if (!FnStartLoc.isValid())
8222 return Error(L,
".fnstart must precede .pad directive");
8223 if (HandlerDataLoc.isValid())
8224 return Error(L,
".pad must precede .handlerdata directive");
8229 return Error(Parser.getTok().getLoc(),
"'#' expected");
8233 const MCExpr *OffsetExpr;
8234 SMLoc ExLoc = Parser.getTok().getLoc();
8236 if (getParser().parseExpression(OffsetExpr, EndLoc))
8237 return Error(ExLoc,
"malformed pad offset");
8240 return Error(ExLoc,
"pad offset must be an immediate");
8242 getTargetStreamer().emitPad(CE->
getValue());
8249 bool ARMAsmParser::parseDirectiveRegSave(
SMLoc L,
bool IsVector) {
8251 if (!FnStartLoc.isValid())
8252 return Error(L,
".fnstart must precede .save or .vsave directives");
8253 if (HandlerDataLoc.isValid())
8254 return Error(L,
".save or .vsave must precede .handlerdata directive");
8257 struct CleanupObject {
8260 for (
unsigned I = 0, E = Operands.
size(); I != E; ++
I)
8266 if (parseRegisterList(CO.Operands))
8268 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8269 if (!IsVector && !Op->isRegList())
8270 return Error(L,
".save expects GPR registers");
8271 if (IsVector && !Op->isDPRRegList())
8272 return Error(L,
".vsave expects DPR registers");
8274 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8284 #define GET_REGISTER_MATCHER
8285 #define GET_SUBTARGET_FEATURE_NAME
8286 #define GET_MATCHER_IMPLEMENTATION
8287 #include "ARMGenAsmMatcher.inc"
8293 ARMOperand *Op =
static_cast<ARMOperand*
>(AsmOp);
8297 if (Kind == MCK__35_0 && Op->isImm()) {
8300 return Match_InvalidOperand;
8302 return Match_Success;
8304 return Match_InvalidOperand;
static bool isReg(const MCInst &MI, unsigned OpNo)
void push_back(const T &Elt)
const char * getPointer() const
size_t size() const
size - Get the string size.
static MCOperand CreateReg(unsigned Reg)
static const fltSemantics IEEEdouble
static const MCConstantExpr * Create(int64_t Value, MCContext &Ctx)
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser. The extension should use the AsmParser i...
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g. ARM instructions which can set condition cod...
An abstraction for memory operations.
MCTargetAsmParser - Generic interface to target specific assembly parsers.
enable_if_c<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT)
size_t find(char C, size_t From=0) const
static unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
StringRef getString() const
static MCOperand CreateExpr(const MCExpr *Val)
StringRef substr(size_t Start, size_t N=npos) const
iterator find(StringRef Key)
iterator insert(iterator I, const T &Elt)
bool isNot(TokenKind K) const
virtual void EmitInstruction(const MCInst &Inst)=0
static const char * getShiftOpcStr(ShiftOpc Op)
StringSwitch & Case(const char(&S)[N], const T &Value)
static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, unsigned VariantID)
static bool instIsBreakpoint(const MCInst &Inst)
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
#define llvm_unreachable(msg)
static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp)
static unsigned MatchRegisterName(StringRef Name)
AsmToken - Target independent representation for an assembler token.
static unsigned getDRegFromQReg(unsigned QReg)
ID
LLVM Calling Convention Representation.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution. It may be set to 'al...
.code16 (X86) / .code 16 (ARM)
unsigned getReg() const
getReg - Returns the register number.
const char * data() const
enable_if_c< std::numeric_limits< T >::is_integer &&!std::numeric_limits< T >::is_signed, std::size_t >::type countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
static int getT2SOImmVal(unsigned Arg)
static int getFP32Imm(const APInt &Imm)
int64_t getIntVal() const
MCRegisterClass - Base class of TargetRegisterClass.
iterator insert(iterator I, const MCOperand &Op)
static bool containsReg(ArrayRef< unsigned > RegUnits, unsigned RegUnit)
Convenient wrapper for checking membership in RegisterOperands. (std::count() doesn't have an early e...
unsigned short NumOperands
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
A switch()-like statement whose cases are string literals.
void array_pod_sort(IteratorTy Start, IteratorTy End)
static unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
* if(!EatIfPresent(lltok::kw_thread_local)) return false
static const char * InstSyncBOptToString(unsigned val)
StringRef trim(StringRef Chars=" \t\n\v\f\r") const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isOptionalDef() const
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value. See class MCOperandInfo.
static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg)
iterator erase(iterator I)
static const ARMMCExpr * Create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
const MCInstrDesc & get(unsigned Opcode) const
static unsigned getNextRegister(unsigned Reg)
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
static const char * ARMCondCodeToString(ARMCC::CondCodes CC)
void setOpcode(unsigned Op)
bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
bool contains(unsigned Reg) const
static bool isDataTypeToken(StringRef Tok)
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
std::string upper() const
Convert the given ASCII string to uppercase.
bool is(TokenKind K) const
static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing)
static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing)
R Default(const T &Value) const
unsigned getOpcode() const
Class for arbitrary precision integers.
static const char * MemBOptToString(unsigned val, bool HasV8)
static unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, unsigned IdxMode=0)
getAM3Opc - This function encodes the addrmode3 opc field.
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(DefaultAlign), cl::values(clEnumValN(DefaultAlign,"arm-default-align","Generate unaligned accesses only on hardware/OS ""combinations that are known to support them"), clEnumValN(StrictAlign,"arm-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"arm-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
static const char * IFlagsToString(unsigned val)
static int getSOImmVal(unsigned Arg)
.code32 (X86) / .code 32 (ARM)
static SMLoc getFromPointer(const char *Ptr)
static bool isARMLowRegister(unsigned Reg)
static CondCodes getOppositeCondition(CondCodes CC)
StringRef getIdentifier() const
static const fltSemantics IEEEsingle
bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
void LLVMInitializeARMAsmParser()
Force static initialization.
static MCOperand CreateImm(int64_t Val)
unsigned getNumOperands() const
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg)
static bool isMem(const MachineInstr *MI, unsigned Op)
#define ARM_FPU_NAME(NAME, ID)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
static unsigned getSORegOffset(unsigned Op)
bool hasSubsectionsViaSymbols() const
bool isFPImm(const APFloat &Val, uint32_t &Imm8Bits)
const MCOperandInfo * OpInfo
void addOperand(const MCOperand &Op)
bool isV8EligibleForIT(InstrType *Instr, int BLXOperandIndex=0)
const MCRegisterInfo & MRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
StringRef slice(size_t Start, size_t End) const
Represents a location in source code.
static float getFPImmFloat(unsigned Imm)
static RegisterPass< NVPTXAllocaHoisting > X("alloca-hoisting","Hoisting alloca instructions in non-entry ""blocks to the entry block")
static const char * getSubtargetFeatureName(unsigned Val)
std::string lower() const
const MCOperand & getOperand(unsigned i) const
static ShiftOpc getSORegShOp(unsigned Op)
bool empty() const
empty - Check if the string is empty.