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MachineCSE.cpp
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1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #define DEBUG_TYPE "machine-cse"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/Debug.h"
29 using namespace llvm;
30 
31 STATISTIC(NumCoalesces, "Number of copies coalesced");
32 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
33 STATISTIC(NumPhysCSEs,
34  "Number of physreg referencing common subexpr eliminated");
35 STATISTIC(NumCrossBBCSEs,
36  "Number of cross-MBB physreg referencing CS eliminated");
37 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
38 
39 namespace {
40  class MachineCSE : public MachineFunctionPass {
41  const TargetInstrInfo *TII;
42  const TargetRegisterInfo *TRI;
43  AliasAnalysis *AA;
46  public:
47  static char ID; // Pass identification
48  MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
50  }
51 
52  virtual bool runOnMachineFunction(MachineFunction &MF);
53 
54  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
55  AU.setPreservesCFG();
61  }
62 
63  virtual void releaseMemory() {
64  ScopeMap.clear();
65  Exps.clear();
66  }
67 
68  private:
69  const unsigned LookAheadLimit;
73  MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
74  typedef ScopedHTType::ScopeTy ScopeType;
76  ScopedHTType VNT;
78  unsigned CurrVN;
79 
80  bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
81  bool isPhysDefTriviallyDead(unsigned Reg,
84  bool hasLivePhysRegDefUses(const MachineInstr *MI,
85  const MachineBasicBlock *MBB,
86  SmallSet<unsigned,8> &PhysRefs,
87  SmallVectorImpl<unsigned> &PhysDefs,
88  bool &PhysUseDef) const;
89  bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
90  SmallSet<unsigned,8> &PhysRefs,
91  SmallVectorImpl<unsigned> &PhysDefs,
92  bool &NonLocal) const;
93  bool isCSECandidate(MachineInstr *MI);
94  bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
95  MachineInstr *CSMI, MachineInstr *MI);
96  void EnterScope(MachineBasicBlock *MBB);
97  void ExitScope(MachineBasicBlock *MBB);
98  bool ProcessBlock(MachineBasicBlock *MBB);
99  void ExitScopeIfDone(MachineDomTreeNode *Node,
101  bool PerformCSE(MachineDomTreeNode *Node);
102  };
103 } // end anonymous namespace
104 
105 char MachineCSE::ID = 0;
107 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
108  "Machine Common Subexpression Elimination", false, false)
111 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
112  "Machine Common Subexpression Elimination", false, false)
113 
114 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
115  MachineBasicBlock *MBB) {
116  bool Changed = false;
117  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
118  MachineOperand &MO = MI->getOperand(i);
119  if (!MO.isReg() || !MO.isUse())
120  continue;
121  unsigned Reg = MO.getReg();
123  continue;
124  if (!MRI->hasOneNonDBGUse(Reg))
125  // Only coalesce single use copies. This ensure the copy will be
126  // deleted.
127  continue;
128  MachineInstr *DefMI = MRI->getVRegDef(Reg);
129  if (!DefMI->isCopy())
130  continue;
131  unsigned SrcReg = DefMI->getOperand(1).getReg();
133  continue;
134  if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
135  continue;
136  if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
137  continue;
138  DEBUG(dbgs() << "Coalescing: " << *DefMI);
139  DEBUG(dbgs() << "*** to: " << *MI);
140  MO.setReg(SrcReg);
141  MRI->clearKillFlags(SrcReg);
142  DefMI->eraseFromParent();
143  ++NumCoalesces;
144  Changed = true;
145  }
146 
147  return Changed;
148 }
149 
150 bool
151 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
154  unsigned LookAheadLeft = LookAheadLimit;
155  while (LookAheadLeft) {
156  // Skip over dbg_value's.
157  while (I != E && I->isDebugValue())
158  ++I;
159 
160  if (I == E)
161  // Reached end of block, register is obviously dead.
162  return true;
163 
164  bool SeenDef = false;
165  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
166  const MachineOperand &MO = I->getOperand(i);
167  if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
168  SeenDef = true;
169  if (!MO.isReg() || !MO.getReg())
170  continue;
171  if (!TRI->regsOverlap(MO.getReg(), Reg))
172  continue;
173  if (MO.isUse())
174  // Found a use!
175  return false;
176  SeenDef = true;
177  }
178  if (SeenDef)
179  // See a def of Reg (or an alias) before encountering any use, it's
180  // trivially dead.
181  return true;
182 
183  --LookAheadLeft;
184  ++I;
185  }
186  return false;
187 }
188 
189 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
190 /// physical registers (except for dead defs of physical registers). It also
191 /// returns the physical register def by reference if it's the only one and the
192 /// instruction does not uses a physical register.
193 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
194  const MachineBasicBlock *MBB,
195  SmallSet<unsigned,8> &PhysRefs,
196  SmallVectorImpl<unsigned> &PhysDefs,
197  bool &PhysUseDef) const{
198  // First, add all uses to PhysRefs.
199  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
200  const MachineOperand &MO = MI->getOperand(i);
201  if (!MO.isReg() || MO.isDef())
202  continue;
203  unsigned Reg = MO.getReg();
204  if (!Reg)
205  continue;
207  continue;
208  // Reading constant physregs is ok.
209  if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
210  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
211  PhysRefs.insert(*AI);
212  }
213 
214  // Next, collect all defs into PhysDefs. If any is already in PhysRefs
215  // (which currently contains only uses), set the PhysUseDef flag.
216  PhysUseDef = false;
218  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
219  const MachineOperand &MO = MI->getOperand(i);
220  if (!MO.isReg() || !MO.isDef())
221  continue;
222  unsigned Reg = MO.getReg();
223  if (!Reg)
224  continue;
226  continue;
227  // Check against PhysRefs even if the def is "dead".
228  if (PhysRefs.count(Reg))
229  PhysUseDef = true;
230  // If the def is dead, it's ok. But the def may not marked "dead". That's
231  // common since this pass is run before livevariables. We can scan
232  // forward a few instructions and check if it is obviously dead.
233  if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
234  PhysDefs.push_back(Reg);
235  }
236 
237  // Finally, add all defs to PhysRefs as well.
238  for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
239  for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
240  PhysRefs.insert(*AI);
241 
242  return !PhysRefs.empty();
243 }
244 
245 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
246  SmallSet<unsigned,8> &PhysRefs,
247  SmallVectorImpl<unsigned> &PhysDefs,
248  bool &NonLocal) const {
249  // For now conservatively returns false if the common subexpression is
250  // not in the same basic block as the given instruction. The only exception
251  // is if the common subexpression is in the sole predecessor block.
252  const MachineBasicBlock *MBB = MI->getParent();
253  const MachineBasicBlock *CSMBB = CSMI->getParent();
254 
255  bool CrossMBB = false;
256  if (CSMBB != MBB) {
257  if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
258  return false;
259 
260  for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
261  if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
262  // Avoid extending live range of physical registers if they are
263  //allocatable or reserved.
264  return false;
265  }
266  CrossMBB = true;
267  }
271  unsigned LookAheadLeft = LookAheadLimit;
272  while (LookAheadLeft) {
273  // Skip over dbg_value's.
274  while (I != E && I != EE && I->isDebugValue())
275  ++I;
276 
277  if (I == EE) {
278  assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
279  (void)CrossMBB;
280  CrossMBB = false;
281  NonLocal = true;
282  I = MBB->begin();
283  EE = MBB->end();
284  continue;
285  }
286 
287  if (I == E)
288  return true;
289 
290  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
291  const MachineOperand &MO = I->getOperand(i);
292  // RegMasks go on instructions like calls that clobber lots of physregs.
293  // Don't attempt to CSE across such an instruction.
294  if (MO.isRegMask())
295  return false;
296  if (!MO.isReg() || !MO.isDef())
297  continue;
298  unsigned MOReg = MO.getReg();
300  continue;
301  if (PhysRefs.count(MOReg))
302  return false;
303  }
304 
305  --LookAheadLeft;
306  ++I;
307  }
308 
309  return false;
310 }
311 
312 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
313  if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
314  MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
315  return false;
316 
317  // Ignore copies.
318  if (MI->isCopyLike())
319  return false;
320 
321  // Ignore stuff that we obviously can't move.
322  if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
324  return false;
325 
326  if (MI->mayLoad()) {
327  // Okay, this instruction does a load. As a refinement, we allow the target
328  // to decide whether the loaded value is actually a constant. If so, we can
329  // actually use it as a load.
330  if (!MI->isInvariantLoad(AA))
331  // FIXME: we should be able to hoist loads with no other side effects if
332  // there are no other instructions which can change memory in this loop.
333  // This is a trivial form of alias analysis.
334  return false;
335  }
336  return true;
337 }
338 
339 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
340 /// common expression that defines Reg.
341 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
342  MachineInstr *CSMI, MachineInstr *MI) {
343  // FIXME: Heuristics that works around the lack the live range splitting.
344 
345  // If CSReg is used at all uses of Reg, CSE should not increase register
346  // pressure of CSReg.
347  bool MayIncreasePressure = true;
350  MayIncreasePressure = false;
352  for (MachineRegisterInfo::use_nodbg_iterator I =MRI->use_nodbg_begin(CSReg),
353  E = MRI->use_nodbg_end(); I != E; ++I) {
354  MachineInstr *Use = &*I;
355  CSUses.insert(Use);
356  }
357  for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
358  E = MRI->use_nodbg_end(); I != E; ++I) {
359  MachineInstr *Use = &*I;
360  if (!CSUses.count(Use)) {
361  MayIncreasePressure = true;
362  break;
363  }
364  }
365  }
366  if (!MayIncreasePressure) return true;
367 
368  // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
369  // an immediate predecessor. We don't want to increase register pressure and
370  // end up causing other computation to be spilled.
371  if (MI->isAsCheapAsAMove()) {
372  MachineBasicBlock *CSBB = CSMI->getParent();
373  MachineBasicBlock *BB = MI->getParent();
374  if (CSBB != BB && !CSBB->isSuccessor(BB))
375  return false;
376  }
377 
378  // Heuristics #2: If the expression doesn't not use a vr and the only use
379  // of the redundant computation are copies, do not cse.
380  bool HasVRegUse = false;
381  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
382  const MachineOperand &MO = MI->getOperand(i);
383  if (MO.isReg() && MO.isUse() &&
385  HasVRegUse = true;
386  break;
387  }
388  }
389  if (!HasVRegUse) {
390  bool HasNonCopyUse = false;
391  for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
392  E = MRI->use_nodbg_end(); I != E; ++I) {
393  MachineInstr *Use = &*I;
394  // Ignore copies.
395  if (!Use->isCopyLike()) {
396  HasNonCopyUse = true;
397  break;
398  }
399  }
400  if (!HasNonCopyUse)
401  return false;
402  }
403 
404  // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
405  // it unless the defined value is already used in the BB of the new use.
406  bool HasPHI = false;
408  for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
409  E = MRI->use_nodbg_end(); I != E; ++I) {
410  MachineInstr *Use = &*I;
411  HasPHI |= Use->isPHI();
412  CSBBs.insert(Use->getParent());
413  }
414 
415  if (!HasPHI)
416  return true;
417  return CSBBs.count(MI->getParent());
418 }
419 
420 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
421  DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
422  ScopeType *Scope = new ScopeType(VNT);
423  ScopeMap[MBB] = Scope;
424 }
425 
426 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
427  DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
429  assert(SI != ScopeMap.end());
430  delete SI->second;
431  ScopeMap.erase(SI);
432 }
433 
434 bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
435  bool Changed = false;
436 
438  SmallVector<unsigned, 2> ImplicitDefsToUpdate;
439  for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
440  MachineInstr *MI = &*I;
441  ++I;
442 
443  if (!isCSECandidate(MI))
444  continue;
445 
446  bool FoundCSE = VNT.count(MI);
447  if (!FoundCSE) {
448  // Look for trivial copy coalescing opportunities.
449  if (PerformTrivialCoalescing(MI, MBB)) {
450  Changed = true;
451 
452  // After coalescing MI itself may become a copy.
453  if (MI->isCopyLike())
454  continue;
455  FoundCSE = VNT.count(MI);
456  }
457  }
458 
459  // Commute commutable instructions.
460  bool Commuted = false;
461  if (!FoundCSE && MI->isCommutable()) {
462  MachineInstr *NewMI = TII->commuteInstruction(MI);
463  if (NewMI) {
464  Commuted = true;
465  FoundCSE = VNT.count(NewMI);
466  if (NewMI != MI) {
467  // New instruction. It doesn't need to be kept.
468  NewMI->eraseFromParent();
469  Changed = true;
470  } else if (!FoundCSE)
471  // MI was changed but it didn't help, commute it back!
472  (void)TII->commuteInstruction(MI);
473  }
474  }
475 
476  // If the instruction defines physical registers and the values *may* be
477  // used, then it's not safe to replace it with a common subexpression.
478  // It's also not safe if the instruction uses physical registers.
479  bool CrossMBBPhysDef = false;
480  SmallSet<unsigned, 8> PhysRefs;
481  SmallVector<unsigned, 2> PhysDefs;
482  bool PhysUseDef = false;
483  if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
484  PhysDefs, PhysUseDef)) {
485  FoundCSE = false;
486 
487  // ... Unless the CS is local or is in the sole predecessor block
488  // and it also defines the physical register which is not clobbered
489  // in between and the physical register uses were not clobbered.
490  // This can never be the case if the instruction both uses and
491  // defines the same physical register, which was detected above.
492  if (!PhysUseDef) {
493  unsigned CSVN = VNT.lookup(MI);
494  MachineInstr *CSMI = Exps[CSVN];
495  if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
496  FoundCSE = true;
497  }
498  }
499 
500  if (!FoundCSE) {
501  VNT.insert(MI, CurrVN++);
502  Exps.push_back(MI);
503  continue;
504  }
505 
506  // Found a common subexpression, eliminate it.
507  unsigned CSVN = VNT.lookup(MI);
508  MachineInstr *CSMI = Exps[CSVN];
509  DEBUG(dbgs() << "Examining: " << *MI);
510  DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
511 
512  // Check if it's profitable to perform this CSE.
513  bool DoCSE = true;
514  unsigned NumDefs = MI->getDesc().getNumDefs() +
515  MI->getDesc().getNumImplicitDefs();
516 
517  for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
518  MachineOperand &MO = MI->getOperand(i);
519  if (!MO.isReg() || !MO.isDef())
520  continue;
521  unsigned OldReg = MO.getReg();
522  unsigned NewReg = CSMI->getOperand(i).getReg();
523 
524  // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
525  // we should make sure it is not dead at CSMI.
526  if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
527  ImplicitDefsToUpdate.push_back(i);
528  if (OldReg == NewReg) {
529  --NumDefs;
530  continue;
531  }
532 
533  assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
535  "Do not CSE physical register defs!");
536 
537  if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
538  DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
539  DoCSE = false;
540  break;
541  }
542 
543  // Don't perform CSE if the result of the old instruction cannot exist
544  // within the register class of the new instruction.
545  const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
546  if (!MRI->constrainRegClass(NewReg, OldRC)) {
547  DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
548  DoCSE = false;
549  break;
550  }
551 
552  CSEPairs.push_back(std::make_pair(OldReg, NewReg));
553  --NumDefs;
554  }
555 
556  // Actually perform the elimination.
557  if (DoCSE) {
558  for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
559  MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
560  MRI->clearKillFlags(CSEPairs[i].second);
561  }
562 
563  // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
564  // we should make sure it is not dead at CSMI.
565  for (unsigned i = 0, e = ImplicitDefsToUpdate.size(); i != e; ++i)
566  CSMI->getOperand(ImplicitDefsToUpdate[i]).setIsDead(false);
567 
568  if (CrossMBBPhysDef) {
569  // Add physical register defs now coming in from a predecessor to MBB
570  // livein list.
571  while (!PhysDefs.empty()) {
572  unsigned LiveIn = PhysDefs.pop_back_val();
573  if (!MBB->isLiveIn(LiveIn))
574  MBB->addLiveIn(LiveIn);
575  }
576  ++NumCrossBBCSEs;
577  }
578 
579  MI->eraseFromParent();
580  ++NumCSEs;
581  if (!PhysRefs.empty())
582  ++NumPhysCSEs;
583  if (Commuted)
584  ++NumCommutes;
585  Changed = true;
586  } else {
587  VNT.insert(MI, CurrVN++);
588  Exps.push_back(MI);
589  }
590  CSEPairs.clear();
591  ImplicitDefsToUpdate.clear();
592  }
593 
594  return Changed;
595 }
596 
597 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
598 /// dominator tree node if its a leaf or all of its children are done. Walk
599 /// up the dominator tree to destroy ancestors which are now done.
600 void
601 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
603  if (OpenChildren[Node])
604  return;
605 
606  // Pop scope.
607  ExitScope(Node->getBlock());
608 
609  // Now traverse upwards to pop ancestors whose offsprings are all done.
610  while (MachineDomTreeNode *Parent = Node->getIDom()) {
611  unsigned Left = --OpenChildren[Parent];
612  if (Left != 0)
613  break;
614  ExitScope(Parent->getBlock());
615  Node = Parent;
616  }
617 }
618 
619 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
623 
624  CurrVN = 0;
625 
626  // Perform a DFS walk to determine the order of visit.
627  WorkList.push_back(Node);
628  do {
629  Node = WorkList.pop_back_val();
630  Scopes.push_back(Node);
631  const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
632  unsigned NumChildren = Children.size();
633  OpenChildren[Node] = NumChildren;
634  for (unsigned i = 0; i != NumChildren; ++i) {
635  MachineDomTreeNode *Child = Children[i];
636  WorkList.push_back(Child);
637  }
638  } while (!WorkList.empty());
639 
640  // Now perform CSE.
641  bool Changed = false;
642  for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
643  MachineDomTreeNode *Node = Scopes[i];
644  MachineBasicBlock *MBB = Node->getBlock();
645  EnterScope(MBB);
646  Changed |= ProcessBlock(MBB);
647  // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
648  ExitScopeIfDone(Node, OpenChildren);
649  }
650 
651  return Changed;
652 }
653 
654 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
655  TII = MF.getTarget().getInstrInfo();
656  TRI = MF.getTarget().getRegisterInfo();
657  MRI = &MF.getRegInfo();
658  AA = &getAnalysis<AliasAnalysis>();
659  DT = &getAnalysis<MachineDominatorTree>();
660  return PerformCSE(DT->getRootNode());
661 }
bool isImplicit() const
void push_back(const T &Elt)
Definition: SmallVector.h:236
const MachineFunction * getParent() const
AnalysisUsage & addPreserved()
static PassRegistry * getPassRegistry()
STATISTIC(NumCoalesces,"Number of copies coalesced")
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:528
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions. Register definitions always occur...
Definition: MCInstrDesc.h:198
void initializeMachineCSEPass(PassRegistry &)
bool mayStore(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:479
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
bool insert(PtrType Ptr)
Definition: SmallPtrSet.h:253
void addLiveIn(unsigned Reg)
const MCInstrDesc & getDesc() const
Definition: MachineInstr.h:257
void setIsDead(bool Val=true)
bool isTerminator(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:366
DomTreeNodeBase< NodeT > * getIDom() const
Definition: Dominators.h:83
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:167
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:648
T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val()
Definition: SmallVector.h:430
Definition: Use.h:60
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:172
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:465
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
unsigned getNumOperands() const
Definition: MachineInstr.h:265
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:106
bool count(PtrType Ptr) const
count - Return true if the specified pointer is in the set.
Definition: SmallPtrSet.h:264
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:56
machine cse
Definition: MachineCSE.cpp:111
bool isCopyLike() const
Definition: MachineInstr.h:678
AnalysisUsage & addPreservedID(const void *ID)
bool insert(const T &V)
Definition: SmallSet.h:59
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:211
NodeT * getBlock() const
Definition: Dominators.h:82
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:119
bool isDebugValue() const
Definition: MachineInstr.h:639
bool isImplicitDef() const
Definition: MachineInstr.h:650
bundle_iterator< MachineInstr, instr_iterator > iterator
machine Machine Common Subexpression Elimination
Definition: MachineCSE.cpp:111
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value. See class MCOperandInfo.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Definition: MachineInstr.h:560
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:267
bool isCopy() const
Definition: MachineInstr.h:669
ItTy next(ItTy it, Dist n)
Definition: STLExtras.h:154
bool hasUnmodeledSideEffects() const
bool isInvariantLoad(AliasAnalysis *AA) const
bool isLabel() const
Definition: MachineInstr.h:628
#define INITIALIZE_AG_DEPENDENCY(depName)
Definition: PassSupport.h:169
unsigned getSubReg() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const std::vector< DomTreeNodeBase< NodeT > * > & getChildren() const
Definition: Dominators.h:84
machine Machine Common Subexpression false
Definition: MachineCSE.cpp:111
virtual const TargetInstrInfo * getInstrInfo() const
bool isInlineAsm() const
Definition: MachineInstr.h:651
bool isSuccessor(const MachineBasicBlock *MBB) const
bool isKill() const
Definition: MachineInstr.h:649
void setPreservesCFG()
Definition: Pass.cpp:249
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
Definition: Debug.cpp:101
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
StringRef getName() const
bool count(const T &V) const
count - Return true if the element is in the set.
Definition: SmallSet.h:48
bundle_iterator< const MachineInstr, const_instr_iterator > const_iterator
bool isLiveIn(unsigned Reg) const
MachineRegisterInfo & getRegInfo()
virtual void getAnalysisUsage(AnalysisUsage &AU) const
void setReg(unsigned Reg)
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:349
const TargetMachine & getTarget() const
virtual const TargetRegisterInfo * getRegisterInfo() const
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Definition: MachineInstr.h:502
#define DEBUG(X)
Definition: Debug.h:97
INITIALIZE_PASS_BEGIN(MachineCSE,"machine-cse","Machine Common Subexpression Elimination", false, false) INITIALIZE_PASS_END(MachineCSE
const MCRegisterInfo & MRI
bool empty() const
Definition: SmallSet.h:42
iterator find(const KeyT &Val)
Definition: DenseMap.h:108
unsigned pred_size() const