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Mips16InstrInfo.cpp
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1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 #include "Mips16InstrInfo.h"
15 #include "MipsMachineFunction.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringRef.h"
22 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/Support/Debug.h"
27 #include <cctype>
28 
29 using namespace llvm;
30 
32  "mips16-never-use-save-restore",
33  cl::init(false),
34  cl::desc("For testing ability to adjust stack pointer "
35  "without save/restore instruction"),
36  cl::Hidden);
37 
38 
40  : MipsInstrInfo(tm, Mips::Bimm16),
41  RI(*tm.getSubtargetImpl()) {}
42 
44  return RI;
45 }
46 
47 /// isLoadFromStackSlot - If the specified machine instruction is a direct
48 /// load from a stack slot, return the virtual or physical register number of
49 /// the destination along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than loading from the stack slot.
52 unsigned Mips16InstrInfo::
54 {
55  return 0;
56 }
57 
58 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 /// store to a stack slot, return the virtual or physical register number of
60 /// the source reg along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than storing to the stack slot.
63 unsigned Mips16InstrInfo::
65 {
66  return 0;
67 }
68 
71  unsigned DestReg, unsigned SrcReg,
72  bool KillSrc) const {
73  unsigned Opc = 0;
74 
75  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
76  Mips::GPR32RegClass.contains(SrcReg))
77  Opc = Mips::MoveR3216;
78  else if (Mips::GPR32RegClass.contains(DestReg) &&
79  Mips::CPU16RegsRegClass.contains(SrcReg))
80  Opc = Mips::Move32R16;
81  else if ((SrcReg == Mips::HI0) &&
82  (Mips::CPU16RegsRegClass.contains(DestReg)))
83  Opc = Mips::Mfhi16, SrcReg = 0;
84 
85  else if ((SrcReg == Mips::LO0) &&
86  (Mips::CPU16RegsRegClass.contains(DestReg)))
87  Opc = Mips::Mflo16, SrcReg = 0;
88 
89 
90  assert(Opc && "Cannot copy registers");
91 
92  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
93 
94  if (DestReg)
95  MIB.addReg(DestReg, RegState::Define);
96 
97  if (SrcReg)
98  MIB.addReg(SrcReg, getKillRegState(KillSrc));
99 }
100 
103  unsigned SrcReg, bool isKill, int FI,
104  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
105  int64_t Offset) const {
106  DebugLoc DL;
107  if (I != MBB.end()) DL = I->getDebugLoc();
109  unsigned Opc = 0;
110  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
111  Opc = Mips::SwRxSpImmX16;
112  assert(Opc && "Register class not handled!");
113  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
114  addFrameIndex(FI).addImm(Offset)
115  .addMemOperand(MMO);
116 }
117 
120  unsigned DestReg, int FI, const TargetRegisterClass *RC,
121  const TargetRegisterInfo *TRI, int64_t Offset) const {
122  DebugLoc DL;
123  if (I != MBB.end()) DL = I->getDebugLoc();
125  unsigned Opc = 0;
126 
127  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
128  Opc = Mips::LwRxSpImmX16;
129  assert(Opc && "Register class not handled!");
130  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
131  .addMemOperand(MMO);
132 }
133 
135  MachineBasicBlock &MBB = *MI->getParent();
136  switch(MI->getDesc().getOpcode()) {
137  default:
138  return false;
139  case Mips::RetRA16:
140  ExpandRetRA16(MBB, MI, Mips::JrcRa16);
141  break;
142  }
143 
144  MBB.erase(MI);
145  return true;
146 }
147 
148 /// GetOppositeBranchOpc - Return the inverse of the specified
149 /// opcode, e.g. turning BEQ to BNE.
150 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
151  switch (Opc) {
152  default: llvm_unreachable("Illegal opcode!");
153  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
154  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
155  case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
156  case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
157  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
158  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
159  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
160  case Mips::Btnez16: return Mips::Bteqz16;
161  case Mips::BtnezX16: return Mips::BteqzX16;
162  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
163  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
164  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
165  case Mips::Bteqz16: return Mips::Btnez16;
166  case Mips::BteqzX16: return Mips::BtnezX16;
167  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
168  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
169  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
170  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
171  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
172  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
173  }
174  assert(false && "Implement this function.");
175  return 0;
176 }
177 
178 // Adjust SP by FrameSize bytes. Save RA, S0, S1
179 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
180  MachineBasicBlock &MBB,
182  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
183  if (!NeverUseSaveRestore) {
184  if (isUInt<11>(FrameSize))
185  BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
186  else {
187  int Base = 2040; // should create template function like isUInt that
188  // returns largest possible n bit unsigned integer
189  int64_t Remainder = FrameSize - Base;
190  BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
191  if (isInt<16>(-Remainder))
192  BuildAddiuSpImm(MBB, I, -Remainder);
193  else
194  adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
195  }
196 
197  }
198  else {
199  //
200  // sw ra, -4[sp]
201  // sw s1, -8[sp]
202  // sw s0, -12[sp]
203 
204  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
205  Mips::RA);
206  MIB1.addReg(Mips::SP);
207  MIB1.addImm(-4);
208  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
209  Mips::S1);
210  MIB2.addReg(Mips::SP);
211  MIB2.addImm(-8);
212  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16),
213  Mips::S0);
214  MIB3.addReg(Mips::SP);
215  MIB3.addImm(-12);
216  adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1);
217  }
218 }
219 
220 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
221 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
222  MachineBasicBlock &MBB,
224  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
225  if (!NeverUseSaveRestore) {
226  if (isUInt<11>(FrameSize))
227  BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
228  else {
229  int Base = 2040; // should create template function like isUInt that
230  // returns largest possible n bit unsigned integer
231  int64_t Remainder = FrameSize - Base;
232  if (isInt<16>(Remainder))
233  BuildAddiuSpImm(MBB, I, Remainder);
234  else
235  adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
236  BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
237  }
238  }
239  else {
240  adjustStackPtrBig(SP, FrameSize, MBB, I, Mips::A0, Mips::A1);
241  // lw ra, -4[sp]
242  // lw s1, -8[sp]
243  // lw s0, -12[sp]
244  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
245  Mips::A0);
246  MIB1.addReg(Mips::SP);
247  MIB1.addImm(-4);
248  MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
249  Mips::RA);
250  MIB0.addReg(Mips::A0);
251  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
252  Mips::S1);
253  MIB2.addReg(Mips::SP);
254  MIB2.addImm(-8);
255  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16),
256  Mips::S0);
257  MIB3.addReg(Mips::SP);
258  MIB3.addImm(-12);
259  }
260 
261 }
262 
263 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
264 // This can only be called at times that we know that there is at least one free
265 // register.
266 // This is clearly safe at prologue and epilogue.
267 //
268 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
269  MachineBasicBlock &MBB,
271  unsigned Reg1, unsigned Reg2) const {
272  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
273 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
274 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
275 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
276  //
277  // li reg1, constant
278  // move reg2, sp
279  // add reg1, reg1, reg2
280  // move sp, reg1
281  //
282  //
283  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
284  MIB1.addImm(Amount);
285  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
286  MIB2.addReg(Mips::SP, RegState::Kill);
287  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
288  MIB3.addReg(Reg1);
289  MIB3.addReg(Reg2, RegState::Kill);
290  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
291  Mips::SP);
292  MIB4.addReg(Reg1, RegState::Kill);
293 }
294 
295 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
296  MachineBasicBlock &MBB,
297  MachineBasicBlock::iterator I) const {
298  assert(false && "adjust stack pointer amount exceeded");
299 }
300 
301 /// Adjust SP by Amount bytes.
302 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
303  MachineBasicBlock &MBB,
304  MachineBasicBlock::iterator I) const {
305  if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
306  BuildAddiuSpImm(MBB, I, Amount);
307  else
308  adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
309 }
310 
311 /// This function generates the sequence of instructions needed to get the
312 /// result of adding register REG and immediate IMM.
313 unsigned
315  int64_t Imm, MachineBasicBlock &MBB,
317  unsigned &NewImm) const {
318  //
319  // given original instruction is:
320  // Instr rx, T[offset] where offset is too big.
321  //
322  // lo = offset & 0xFFFF
323  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
324  //
325  // let T = temporary register
326  // li T, hi
327  // shl T, 16
328  // add T, Rx, T
329  //
330  RegScavenger rs;
331  int32_t lo = Imm & 0xFFFF;
332  NewImm = lo;
333  int Reg =0;
334  int SpReg = 0;
335 
336  rs.enterBasicBlock(&MBB);
337  rs.forward(II);
338  //
339  // We need to know which registers can be used, in the case where there
340  // are not enough free registers. We exclude all registers that
341  // are used in the instruction that we are helping.
342  // // Consider all allocatable registers in the register class initially
343  BitVector Candidates =
344  RI.getAllocatableSet
345  (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
346  // Exclude all the registers being used by the instruction.
347  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
348  MachineOperand &MO = II->getOperand(i);
349  if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
351  Candidates.reset(MO.getReg());
352  }
353  //
354  // If the same register was used and defined in an instruction, then
355  // it will not be in the list of candidates.
356  //
357  // we need to analyze the instruction that we are helping.
358  // we need to know if it defines register x but register x is not
359  // present as an operand of the instruction. this tells
360  // whether the register is live before the instruction. if it's not
361  // then we don't need to save it in case there are no free registers.
362  //
363  int DefReg = 0;
364  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
365  MachineOperand &MO = II->getOperand(i);
366  if (MO.isReg() && MO.isDef()) {
367  DefReg = MO.getReg();
368  break;
369  }
370  }
371  //
372  BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
373 
374  Available &= Candidates;
375  //
376  // we use T0 for the first register, if we need to save something away.
377  // we use T1 for the second register, if we need to save something away.
378  //
379  unsigned FirstRegSaved =0, SecondRegSaved=0;
380  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
381 
382 
383  Reg = Available.find_first();
384 
385  if (Reg == -1) {
386  Reg = Candidates.find_first();
387  Candidates.reset(Reg);
388  if (DefReg != Reg) {
389  FirstRegSaved = Reg;
390  FirstRegSavedTo = Mips::T0;
391  copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
392  }
393  }
394  else
395  Available.reset(Reg);
396  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
397  NewImm = 0;
398  if (FrameReg == Mips::SP) {
399  SpReg = Available.find_first();
400  if (SpReg == -1) {
401  SpReg = Candidates.find_first();
402  // Candidates.reset(SpReg); // not really needed
403  if (DefReg!= SpReg) {
404  SecondRegSaved = SpReg;
405  SecondRegSavedTo = Mips::T1;
406  }
407  if (SecondRegSaved)
408  copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
409  }
410  else
411  Available.reset(SpReg);
412  copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
413  BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
414  .addReg(Reg);
415  }
416  else
417  BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
418  .addReg(Reg, RegState::Kill);
419  if (FirstRegSaved || SecondRegSaved) {
420  II = llvm::next(II);
421  if (FirstRegSaved)
422  copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
423  if (SecondRegSaved)
424  copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
425  }
426  return Reg;
427 }
428 
429 /// This function generates the sequence of instructions needed to get the
430 /// result of adding register REG and immediate IMM.
431 unsigned
433  unsigned FrameReg,
434  int64_t Imm, MachineBasicBlock &MBB,
436  unsigned &NewImm) const {
437  const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
438  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
439  unsigned Reg = RegInfo.createVirtualRegister(RC);
440  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm);
441  NewImm = 0;
442  return Reg;
443 }
444 
445 unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
446  return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
447  Opc == Mips::Bimm16 ||
448  Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
449  Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
450  Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
451  Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
452  Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
453  Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
454  Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
455  Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
456  Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
457  Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
458 }
459 
460 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
462  unsigned Opc) const {
463  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
464 }
465 
466 
467 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
468  if (validSpImm8(Imm))
469  return get(Mips::AddiuSpImm16);
470  else
471  return get(Mips::AddiuSpImmX16);
472 }
473 
475  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
476  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
477  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
478 }
479 
481  return new Mips16InstrInfo(TM);
482 }
483 
484 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
485  int64_t Amount) {
486  switch (Opcode) {
487  case Mips::LbRxRyOffMemX16:
488  case Mips::LbuRxRyOffMemX16:
489  case Mips::LhRxRyOffMemX16:
490  case Mips::LhuRxRyOffMemX16:
491  case Mips::SbRxRyOffMemX16:
492  case Mips::ShRxRyOffMemX16:
493  case Mips::LwRxRyOffMemX16:
494  case Mips::SwRxRyOffMemX16:
495  case Mips::SwRxSpImmX16:
496  case Mips::LwRxSpImmX16:
497  return isInt<16>(Amount);
498  case Mips::AddiuRxRyOffMemX16:
499  if ((Reg == Mips::PC) || (Reg == Mips::SP))
500  return isInt<16>(Amount);
501  return isInt<15>(Amount);
502  }
503  llvm_unreachable("unexpected Opcode in validImmediate");
504 }
505 
506 /// Measure the specified inline asm to determine an approximation of its
507 /// length.
508 /// Comments (which run till the next SeparatorString or newline) do not
509 /// count as an instruction.
510 /// Any other non-whitespace text is considered an instruction, with
511 /// multiple instructions separated by SeparatorString or newlines.
512 /// Variable-length instructions are not handled here; this function
513 /// may be overloaded in the target code to do that.
514 /// We implement the special case of the .space directive taking only an
515 /// integer argument, which is the size in bytes. This is used for creating
516 /// inline code spacing for testing purposes using inline assembly.
517 ///
518 unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
519  const MCAsmInfo &MAI) const {
520 
521 
522  // Count the number of instructions in the asm.
523  bool atInsnStart = true;
524  unsigned Length = 0;
525  for (; *Str; ++Str) {
526  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
527  strlen(MAI.getSeparatorString())) == 0)
528  atInsnStart = true;
529  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
530  if (strncmp(Str, ".space", 6)==0) {
531  char *EStr; int Sz;
532  Sz = strtol(Str+6, &EStr, 10);
533  while (isspace(*EStr)) ++EStr;
534  if (*EStr=='\0') {
535  DEBUG(dbgs() << "parsed .space " << Sz << '\n');
536  return Sz;
537  }
538  }
539  Length += MAI.getMaxInstLength();
540  atInsnStart = false;
541  }
542  if (atInsnStart && strncmp(Str, MAI.getCommentString(),
543  strlen(MAI.getCommentString())) == 0)
544  atInsnStart = false;
545  }
546 
547  return Length;
548 }
const MachineFunction * getParent() const
The memory access reads data.
static cl::opt< bool > NeverUseSaveRestore("mips16-never-use-save-restore", cl::init(false), cl::desc("For testing ability to adjust stack pointer ""without save/restore instruction"), cl::Hidden)
instr_iterator erase(instr_iterator I)
int find_first() const
Definition: BitVector.h:159
The memory access writes data.
const MipsInstrInfo * createMips16InstrInfo(MipsTargetMachine &TM)
Create MipsInstrInfo objects.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
long int strtol(const char *nptr, char **endptr, int base);
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
static bool isVirtualRegister(unsigned Reg)
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
#define llvm_unreachable(msg)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
Adjust SP by Amount bytes.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
const MachineInstrBuilder & addImm(int64_t Val) const
void forward()
forward - Move the internal MBB iterator and update register states.
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const
unsigned basicLoadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned &NewImm) const
BitVector getRegsAvailable(const TargetRegisterClass *RC)
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
void enterBasicBlock(MachineBasicBlock *mbb)
unsigned getKillRegState(bool B)
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
bundle_iterator< MachineInstr, instr_iterator > iterator
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:314
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const
ItTy next(ItTy it, Dist n)
Definition: STLExtras.h:154
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
BitVector & reset()
Definition: BitVector.h:275
virtual unsigned getOppositeBranchOpc(unsigned Opc) const
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
static bool validSpImm8(int offset)
const MachineInstrBuilder & addFrameIndex(int Idx) const
size_t strlen(const char *s);
raw_ostream & dbgs()
dbgs - Return a circular-buffered debug stream.
Definition: Debug.cpp:101
virtual const MipsRegisterInfo & getRegisterInfo() const
Mips16InstrInfo(MipsTargetMachine &TM)
MachineRegisterInfo & getRegInfo()
const char * getSeparatorString() const
Definition: MCAsmInfo.h:414
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:272
unsigned getReg() const
getReg - Returns the register number.
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const
unsigned getMaxInstLength() const
Definition: MCAsmInfo.h:405
#define DEBUG(X)
Definition: Debug.h:97
int strncmp(const char *s1, const char *s2, size_t n);
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, unsigned Flag) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
const char * getCommentString() const
Definition: MCAsmInfo.h:420
#define T1