LLVM API Documentation
#include <AArch64ISelLowering.h>
Definition at line 207 of file AArch64ISelLowering.h.
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explicit |
Definition at line 42 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::AND, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::CTPOP, llvm::TargetLoweringBase::Custom, llvm::ISD::DYNAMIC_STACKALLOC, llvm::TargetLoweringBase::Expand, llvm::ISD::EXTLOAD, llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::TargetMachine::getSubtarget(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::AArch64Subtarget::hasFPARMv8(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm::TargetLoweringBase::Legal, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLoweringBase::Promote, llvm::ISD::ROTL, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::TargetLoweringBase::setExceptionPointerRegister(), llvm::TargetLoweringBase::setExceptionSelectorRegister(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UREM, llvm::MVT::v16i8, llvm::MVT::v1f32, llvm::MVT::v1f64, llvm::MVT::v1i16, llvm::MVT::v1i32, llvm::MVT::v1i64, llvm::MVT::v1i8, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::ISD::ZEXTLOAD.
| SDValue AArch64TargetLowering::addTokenForArgument | ( | SDValue | Chain, |
| SelectionDAG & | DAG, | ||
| MachineFrameInfo * | MFI, | ||
| int | ClobberedFI | ||
| ) | const |
Finds the incoming stack arguments which overlap the given fixed stack object and incorporates their load into the current chain. This prevents an upcoming store from clobbering the stack argument before it's used.
Definition at line 1721 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::TokenFactor, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by LowerCall().
| CCAssignFn * AArch64TargetLowering::CCAssignFnForNode | ( | CallingConv::ID | CC | ) | const |
Definition at line 1021 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::C, llvm::CallingConv::Fast, and llvm_unreachable.
Referenced by IsEligibleForTailCallOptimization(), LowerCall(), LowerCallResult(), LowerFormalArguments(), and LowerReturn().
| bool AArch64TargetLowering::DoesCalleeRestoreStack | ( | CallingConv::ID | CallCC, |
| bool | TailCallOpt | ||
| ) | const |
Definition at line 1712 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::Fast.
Referenced by LowerCall(), and LowerFormalArguments().
| MachineBasicBlock * AArch64TargetLowering::emitAtomicBinary | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB, | ||
| unsigned | Size, | ||
| unsigned | Opcode | ||
| ) | const |
Definition at line 407 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineInstr::getDebugLoc(), getExclusiveOperation(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MachineFunction::insert(), MRI, llvm::next(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by EmitInstrWithCustomInserter().
| MachineBasicBlock * AArch64TargetLowering::emitAtomicBinaryMinMax | ( | MachineInstr * | MI, |
| MachineBasicBlock * | BB, | ||
| unsigned | Size, | ||
| unsigned | CmpOp, | ||
| A64CC::CondCodes | Cond | ||
| ) | const |
Definition at line 491 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineInstr::getDebugLoc(), getExclusiveOperation(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MachineFunction::insert(), MRI, llvm::next(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by EmitInstrWithCustomInserter().
| MachineBasicBlock * AArch64TargetLowering::emitAtomicCmpSwap | ( | MachineInstr * | MI, |
| MachineBasicBlock * | BB, | ||
| unsigned | Size | ||
| ) | const |
Definition at line 583 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineInstr::getDebugLoc(), getExclusiveOperation(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MachineFunction::insert(), MRI, llvm::A64CC::NE, llvm::next(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by EmitInstrWithCustomInserter().
| MachineBasicBlock * AArch64TargetLowering::EmitF128CSEL | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB | ||
| ) | const |
Definition at line 663 of file AArch64ISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineFrameInfo::CreateSpillStackObject(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MachineFunction::insert(), llvm::MachineOperand::isKill(), llvm::next(), llvm::A64SysReg::NZCV, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by EmitInstrWithCustomInserter().
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This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow.
Reimplemented from llvm::TargetLowering.
Definition at line 761 of file AArch64ISelLowering.cpp.
References emitAtomicBinary(), emitAtomicBinaryMinMax(), emitAtomicCmpSwap(), EmitF128CSEL(), llvm::MachineInstr::getOpcode(), llvm::A64CC::GT, llvm::A64CC::HI, llvm_unreachable, llvm::A64CC::LO, and llvm::A64CC::LT.
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Given a constraint, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 4332 of file AArch64ISelLowering.cpp.
References llvm::TargetLowering::C_Memory, llvm::TargetLowering::C_Other, llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().
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Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.
Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.
This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer..
Reimplemented from llvm::TargetLowering.
Definition at line 4460 of file AArch64ISelLowering.cpp.
References llvm::MVT::f16, llvm::MVT::f32, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::getSizeInBits(), and llvm::MVT::i64.
| SDValue AArch64TargetLowering::getSelectableIntSetCC | ( | SDValue | LHS, |
| SDValue | RHS, | ||
| ISD::CondCode | CC, | ||
| SDValue & | A64cc, | ||
| SelectionDAG & | DAG, | ||
| SDLoc & | dl | ||
| ) | const |
Definition at line 1781 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::C, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, IntCCToA64CC(), isLegalICmpImmediate(), llvm::ISD::isSignedIntSetCC(), llvm::AArch64ISD::SETCC, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
Referenced by LowerBR_CC(), LowerSELECT_CC(), and LowerSETCC().
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Return the ValueType of the result of SETCC operations. Also used to obtain the target's preferred type for the condition operand of SELECT and BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other since there are no other operands to get a type hint from.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 368 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::MVT::i32, and llvm::EVT::isVector().
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Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.
Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.
Reimplemented from llvm::TargetLowering.
Definition at line 4367 of file AArch64ISelLowering.cpp.
References llvm_unreachable.
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This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 878 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::BFI, llvm::AArch64ISD::BR_CC, llvm::AArch64ISD::Call, llvm::AArch64ISD::EXTR, llvm::AArch64ISD::FPMOV, llvm::AArch64ISD::GOTLoad, llvm::AArch64ISD::NEON_BSL, llvm::AArch64ISD::NEON_CMP, llvm::AArch64ISD::NEON_CMPZ, llvm::AArch64ISD::NEON_FMOVIMM, llvm::AArch64ISD::NEON_LD1_UPD, llvm::AArch64ISD::NEON_LD1x2_UPD, llvm::AArch64ISD::NEON_LD1x3_UPD, llvm::AArch64ISD::NEON_LD1x4_UPD, llvm::AArch64ISD::NEON_LD2_UPD, llvm::AArch64ISD::NEON_LD2DUP, llvm::AArch64ISD::NEON_LD2DUP_UPD, llvm::AArch64ISD::NEON_LD2LN_UPD, llvm::AArch64ISD::NEON_LD3_UPD, llvm::AArch64ISD::NEON_LD3DUP, llvm::AArch64ISD::NEON_LD3DUP_UPD, llvm::AArch64ISD::NEON_LD3LN_UPD, llvm::AArch64ISD::NEON_LD4_UPD, llvm::AArch64ISD::NEON_LD4DUP, llvm::AArch64ISD::NEON_LD4DUP_UPD, llvm::AArch64ISD::NEON_LD4LN_UPD, llvm::AArch64ISD::NEON_MOVIMM, llvm::AArch64ISD::NEON_MVNIMM, llvm::AArch64ISD::NEON_QSHLs, llvm::AArch64ISD::NEON_QSHLu, llvm::AArch64ISD::NEON_REV16, llvm::AArch64ISD::NEON_REV32, llvm::AArch64ISD::NEON_REV64, llvm::AArch64ISD::NEON_ST1_UPD, llvm::AArch64ISD::NEON_ST1x2_UPD, llvm::AArch64ISD::NEON_ST1x3_UPD, llvm::AArch64ISD::NEON_ST1x4_UPD, llvm::AArch64ISD::NEON_ST2_UPD, llvm::AArch64ISD::NEON_ST2LN_UPD, llvm::AArch64ISD::NEON_ST3_UPD, llvm::AArch64ISD::NEON_ST3LN_UPD, llvm::AArch64ISD::NEON_ST4_UPD, llvm::AArch64ISD::NEON_ST4LN_UPD, llvm::AArch64ISD::NEON_TRN1, llvm::AArch64ISD::NEON_TRN2, llvm::AArch64ISD::NEON_TST, llvm::AArch64ISD::NEON_UZP1, llvm::AArch64ISD::NEON_UZP2, llvm::AArch64ISD::NEON_VDUP, llvm::AArch64ISD::NEON_VDUPLANE, llvm::AArch64ISD::NEON_VEXTRACT, llvm::AArch64ISD::NEON_ZIP1, llvm::AArch64ISD::NEON_ZIP2, llvm::AArch64ISD::Ret, llvm::AArch64ISD::SBFX, llvm::AArch64ISD::SELECT_CC, llvm::AArch64ISD::SETCC, llvm::AArch64ISD::TC_RETURN, llvm::AArch64ISD::THREAD_POINTER, llvm::AArch64ISD::TLSDESCCALL, llvm::AArch64ISD::WrapperLarge, and llvm::AArch64ISD::WrapperSmall.
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Represent NEON load and store intrinsics as MemIntrinsicNodes. The associated MachineMemOperands record the alignment specified in the intrinsic calls.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 4492 of file AArch64ISelLowering.cpp.
References llvm::Intrinsic::aarch64_neon_vld1x2, llvm::Intrinsic::aarch64_neon_vld1x3, llvm::Intrinsic::aarch64_neon_vld1x4, llvm::Intrinsic::aarch64_neon_vst1x2, llvm::Intrinsic::aarch64_neon_vst1x3, llvm::Intrinsic::aarch64_neon_vst1x4, llvm::TargetLoweringBase::IntrinsicInfo::align, llvm::Intrinsic::arm_neon_vld1, llvm::Intrinsic::arm_neon_vld2, llvm::Intrinsic::arm_neon_vld2lane, llvm::Intrinsic::arm_neon_vld3, llvm::Intrinsic::arm_neon_vld3lane, llvm::Intrinsic::arm_neon_vld4, llvm::Intrinsic::arm_neon_vld4lane, llvm::Intrinsic::arm_neon_vst1, llvm::Intrinsic::arm_neon_vst2, llvm::Intrinsic::arm_neon_vst2lane, llvm::Intrinsic::arm_neon_vst3, llvm::Intrinsic::arm_neon_vst3lane, llvm::Intrinsic::arm_neon_vst4, llvm::Intrinsic::arm_neon_vst4lane, llvm::CallInst::getArgOperand(), llvm::Type::getContext(), llvm::TargetLoweringBase::getDataLayout(), llvm::CallInst::getNumArgOperands(), llvm::Value::getType(), llvm::DataLayout::getTypeAllocSize(), llvm::EVT::getVectorVT(), llvm::MVT::i64, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::Type::isVectorTy(), llvm::TargetLoweringBase::IntrinsicInfo::memVT, llvm::TargetLoweringBase::IntrinsicInfo::offset, llvm::TargetLoweringBase::IntrinsicInfo::opc, llvm::TargetLoweringBase::IntrinsicInfo::ptrVal, llvm::TargetLoweringBase::IntrinsicInfo::readMem, llvm::TargetLoweringBase::IntrinsicInfo::vol, and llvm::TargetLoweringBase::IntrinsicInfo::writeMem.
| bool AArch64TargetLowering::IsEligibleForTailCallOptimization | ( | SDValue | Callee, |
| CallingConv::ID | CalleeCC, | ||
| bool | IsVarArg, | ||
| bool | IsCalleeStructRet, | ||
| bool | IsCallerStructRet, | ||
| const SmallVectorImpl< ISD::OutputArg > & | Outs, | ||
| const SmallVectorImpl< SDValue > & | OutVals, | ||
| const SmallVectorImpl< ISD::InputArg > & | Ins, | ||
| SelectionDAG & | DAG | ||
| ) | const |
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Targets which want to do tail call optimization should implement this function.
Definition at line 1603 of file AArch64ISelLowering.cpp.
References llvm::CCState::AnalyzeCallOperands(), llvm::CCState::AnalyzeCallResult(), llvm::Function::arg_begin(), llvm::Function::arg_end(), llvm::CallingConv::C, CCAssignFnForNode(), llvm::SmallVectorBase::empty(), llvm::AArch64MachineFunctionInfo::getBytesInStackArgArea(), llvm::Function::getCallingConv(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetOptions::GuaranteedTailCallOpt, IsTailCallConvention(), llvm::TargetMachine::Options, and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by LowerCall().
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3821 of file AArch64ISelLowering.cpp.
References llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), and llvm::MVT::SimpleTy.
| bool AArch64TargetLowering::isKnownShuffleVector | ( | SDValue | Op, |
| SelectionDAG & | DAG, | ||
| SDValue & | Res | ||
| ) | const |
Definition at line 3843 of file AArch64ISelLowering.cpp.
References llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::i64, and LowerVECTOR_SHUFFLE().
Referenced by LowerBUILD_VECTOR().
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Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1770 of file AArch64ISelLowering.cpp.
Referenced by getSelectableIntSetCC().
| bool AArch64TargetLowering::IsTailCallConvention | ( | CallingConv::ID | CallCC | ) | const |
Definition at line 1717 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::Fast.
Referenced by IsEligibleForTailCallOptimization().
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Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.
Reimplemented from llvm::TargetLowering.
Definition at line 4374 of file AArch64ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::CallingConv::C, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getTargetBlockAddress(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetConstantFP(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::A64Imms::isLogicalImm(), llvm_unreachable, and llvm::TargetLowering::LowerAsmOperandForConstraint().
| SDValue llvm::AArch64TargetLowering::LowerATOMIC_FENCE | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
| SDValue llvm::AArch64TargetLowering::LowerATOMIC_STORE | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
| SDValue AArch64TargetLowering::LowerBlockAddress | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 1875 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetBlockAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MVT::i32, llvm::CodeModel::Large, llvm_unreachable, llvm::AArch64II::MO_ABS_G0_NC, llvm::AArch64II::MO_ABS_G1_NC, llvm::AArch64II::MO_ABS_G2_NC, llvm::AArch64II::MO_ABS_G3, llvm::AArch64II::MO_LO12, llvm::AArch64II::MO_NO_FLAG, llvm::CodeModel::Small, llvm::AArch64ISD::WrapperLarge, and llvm::AArch64ISD::WrapperSmall.
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerBR_CC | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 1928 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::BR_CC, llvm::MVT::f128, FPCCToA64CC(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getSelectableIntSetCC(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::A64CC::Invalid, llvm::EVT::isInteger(), llvm::MVT::Other, llvm::AArch64ISD::SETCC, llvm::ISD::SETNE, and llvm::TargetLowering::softenSetCCOperands().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerBRCOND | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 1905 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::AArch64ISD::BR_CC, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::A64CC::NE, llvm::MVT::Other, llvm::AArch64ISD::SETCC, and llvm::ISD::SETNE.
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerBUILD_VECTOR | ( | SDValue | Op, |
| SelectionDAG & | DAG, | ||
| const AArch64Subtarget * | ST | ||
| ) | const |
Definition at line 3897 of file AArch64ISelLowering.cpp.
References llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::begin(), llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZExtValue(), I, llvm::MVT::i32, llvm::MVT::i64, llvm::APFloat::IEEEdouble, llvm::APFloat::IEEEsingle, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::insert(), llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::A64Imms::isFPImm(), isKnownShuffleVector(), isNeonModifiedImm(), llvm::ISD::isNormalLoad(), N, llvm::AArch64ISD::NEON_FMOVIMM, llvm::Neon_Mov_Imm, llvm::AArch64ISD::NEON_MOVIMM, llvm::Neon_Mvn_Imm, llvm::AArch64ISD::NEON_MVNIMM, llvm::AArch64ISD::NEON_VDUP, llvm::AArch64ISD::NEON_VDUPLANE, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::size(), llvm::ISD::UNDEF, llvm::MVT::v2f32, llvm::MVT::v2f64, and llvm::MVT::v4f32.
Referenced by LowerOperation().
|
virtual |
This hook must be implemented to lower calls into the the specified DAG. The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.
Reimplemented from llvm::TargetLowering.
Definition at line 1294 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, addTokenForArgument(), llvm::CCValAssign::AExt, llvm::CCState::AnalyzeCallOperands(), llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, llvm::AArch64ISD::Call, llvm::TargetLowering::CallLoweringInfo::CallConv, llvm::TargetLowering::CallLoweringInfo::Callee, CCAssignFnForNode(), llvm::TargetLowering::CallLoweringInfo::Chain, llvm::MachineFrameInfo::CreateFixedObject(), llvm::TargetLowering::CallLoweringInfo::DAG, llvm::TargetLowering::CallLoweringInfo::DL, DoesCalleeRestoreStack(), llvm::SmallVectorBase::empty(), llvm::CCValAssign::Full, G, llvm::AArch64MachineFunctionInfo::getBytesInStackArgArea(), llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::TargetRegisterInfo::getCallPreservedMask(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getCALLSEQ_START(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getIntPtrConstant(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getMemcpy(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::TargetMachine::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::MVT::getSizeInBits(), llvm::MachinePointerInfo::getStack(), llvm::SelectionDAG::getStore(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::CCValAssign::getValVT(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::TargetOptions::GuaranteedTailCallOpt, llvm::Function::hasStructRetAttr(), llvm::MVT::i32, llvm::MVT::i64, llvm::MipsISD::Ins, llvm::TargetLowering::CallLoweringInfo::Ins, llvm::TargetOpcode::INSERT_SUBREG, llvm::ISD::ArgFlagsTy::isByVal(), IsEligibleForTailCallOptimization(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm::TargetLowering::CallLoweringInfo::IsTailCall, llvm::TargetLowering::CallLoweringInfo::IsVarArg, llvm_unreachable, LowerCallResult(), llvm::X86II::OpSize, llvm::TargetMachine::Options, llvm::MVT::Other, llvm::TargetLowering::CallLoweringInfo::Outs, llvm::TargetLowering::CallLoweringInfo::OutVals, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::RoundUpToAlignment(), llvm::CCValAssign::SExt, llvm::SmallVectorTemplateCommon< T >::size(), llvm::SPII::Store, llvm::AArch64ISD::TC_RETURN, llvm::ISD::TokenFactor, and llvm::CCValAssign::ZExt.
| SDValue AArch64TargetLowering::LowerCallResult | ( | SDValue | Chain, |
| SDValue | InFlag, | ||
| CallingConv::ID | CallConv, | ||
| bool | IsVarArg, | ||
| const SmallVectorImpl< ISD::InputArg > & | Ins, | ||
| SDLoc | dl, | ||
| SelectionDAG & | DAG, | ||
| SmallVectorImpl< SDValue > & | InVals | ||
| ) | const |
Definition at line 1558 of file AArch64ISelLowering.cpp.
References llvm::CCValAssign::AExt, llvm::CCState::AnalyzeCallResult(), llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, CCAssignFnForNode(), llvm::CCValAssign::Full, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValue(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::isRegLoc(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::CCValAssign::SExt, llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::TRUNCATE, and llvm::CCValAssign::ZExt.
Referenced by LowerCall().
| SDValue AArch64TargetLowering::LowerF128ToCall | ( | SDValue | Op, |
| SelectionDAG & | DAG, | ||
| RTLIB::Libcall | Call | ||
| ) | const |
Definition at line 1982 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExternalSymbol(), llvm::TargetLoweringBase::getLibcallCallingConv(), llvm::TargetLoweringBase::getLibcallName(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRoot(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::TargetLowering::isInTailCallPosition(), llvm::TargetLowering::ArgListEntry::isSExt, llvm::TargetLowering::ArgListEntry::isZExt, llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::ArgListEntry::Node, and llvm::TargetLowering::ArgListEntry::Ty.
Referenced by LowerFP_EXTEND(), LowerFP_TO_INT(), LowerINT_TO_FP(), and LowerOperation().
|
virtual |
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.
Reimplemented from llvm::TargetLowering.
Definition at line 1106 of file AArch64ISelLowering.cpp.
References llvm::MachineFunction::addLiveIn(), llvm::CCValAssign::AExt, llvm::CCState::AnalyzeFormalArguments(), llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, CCAssignFnForNode(), DoesCalleeRestoreStack(), llvm::TargetOpcode::EXTRACT_SUBREG, llvm::CCValAssign::Full, llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MVT::getSizeInBits(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstant(), llvm::TargetLoweringBase::getTargetMachine(), llvm::CCValAssign::getValVT(), llvm::TargetOptions::GuaranteedTailCallOpt, llvm::MVT::i32, llvm::ISD::ArgFlagsTy::isByVal(), llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), llvm_unreachable, llvm::TargetMachine::Options, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::RoundUpToAlignment(), SaveVarArgRegisters(), llvm::AArch64MachineFunctionInfo::setArgumentStackToRestore(), llvm::AArch64MachineFunctionInfo::setBytesInStackArgArea(), llvm::CCValAssign::SExt, llvm::SmallVectorTemplateCommon< T >::size(), and llvm::CCValAssign::ZExt.
| SDValue AArch64TargetLowering::LowerFP_EXTEND | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2041 of file AArch64ISelLowering.cpp.
References llvm::MVT::f128, llvm::RTLIB::getFPEXT(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and LowerF128ToCall().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerFP_ROUND | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2026 of file AArch64ISelLowering.cpp.
References llvm::MVT::f128, llvm::RTLIB::getFPROUND(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::TargetLowering::makeLibCall().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerFP_TO_INT | ( | SDValue | Op, |
| SelectionDAG & | DAG, | ||
| bool | IsSigned | ||
| ) | const |
Definition at line 2051 of file AArch64ISelLowering.cpp.
References llvm::MVT::f128, llvm::RTLIB::getFPTOSINT(), llvm::RTLIB::getFPTOUINT(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and LowerF128ToCall().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerFRAMEADDR | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2089 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::MachineFrameInfo::setFrameAddressIsTaken().
Referenced by LowerOperation(), and LowerRETURNADDR().
| SDValue AArch64TargetLowering::LowerGlobalAddressELF | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2213 of file AArch64ISelLowering.cpp.
References llvm::TargetLoweringBase::getTargetMachine(), llvm::CodeModel::Large, llvm_unreachable, LowerGlobalAddressELFLarge(), LowerGlobalAddressELFSmall(), and llvm::CodeModel::Small.
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerGlobalAddressELFLarge | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2107 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::CodeModel::Large, llvm::AArch64II::MO_ABS_G0_NC, llvm::AArch64II::MO_ABS_G1_NC, llvm::AArch64II::MO_ABS_G2_NC, llvm::AArch64II::MO_ABS_G3, llvm::Reloc::Static, and llvm::AArch64ISD::WrapperLarge.
Referenced by LowerGlobalAddressELF().
| SDValue AArch64TargetLowering::LowerGlobalAddressELFSmall | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2132 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::DataLayout::getABITypeAlignment(), llvm::GlobalValue::getAlignment(), llvm::SelectionDAG::getConstant(), llvm::MachinePointerInfo::getConstantPool(), llvm::TargetLoweringBase::getDataLayout(), llvm::SequentialType::getElementType(), llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::TargetLoweringBase::getPointerTy(), llvm::TargetMachine::getRelocationModel(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::AArch64ISD::GOTLoad, llvm::AArch64Subtarget::GVIsIndirectSymbol(), llvm::MVT::i32, llvm::Type::isSized(), llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_GOT_LO12, llvm::AArch64II::MO_LO12, llvm::AArch64II::MO_NO_FLAG, llvm::CodeModel::Small, llvm::Reloc::Static, and llvm::AArch64ISD::WrapperSmall.
Referenced by LowerGlobalAddressELF().
| SDValue AArch64TargetLowering::LowerGlobalTLSAddress | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2273 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TLSModel::GeneralDynamic, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetMachine::getTLSModel(), llvm::AArch64ISD::GOTLoad, llvm::MVT::i32, llvm::MVT::i64, llvm::AArch64MachineFunctionInfo::incNumLocalDynamicTLSAccesses(), llvm::TLSModel::InitialExec, llvm_unreachable, llvm::TLSModel::LocalDynamic, llvm::TLSModel::LocalExec, LowerTLSDescCall(), llvm::AArch64II::MO_DTPREL_G0_NC, llvm::AArch64II::MO_DTPREL_G1, llvm::AArch64II::MO_GOTTPREL, llvm::AArch64II::MO_GOTTPREL_LO12, llvm::AArch64II::MO_TLSDESC, llvm::AArch64II::MO_TLSDESC_LO12, llvm::AArch64II::MO_TPREL_G0_NC, llvm::AArch64II::MO_TPREL_G1, llvm::CodeModel::Small, llvm::AArch64ISD::THREAD_POINTER, and llvm::AArch64ISD::WrapperSmall.
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerINT_TO_FP | ( | SDValue | Op, |
| SelectionDAG & | DAG, | ||
| bool | IsSigned | ||
| ) | const |
Definition at line 2366 of file AArch64ISelLowering.cpp.
References llvm::MVT::f128, llvm::SDValue::getOperand(), llvm::RTLIB::getSINTTOFP(), llvm::RTLIB::getUINTTOFP(), llvm::SDValue::getValueType(), and LowerF128ToCall().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerJumpTable | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2384 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::JumpTableSDNode::getIndex(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetJumpTable(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MVT::i32, llvm::CodeModel::Large, llvm_unreachable, llvm::AArch64II::MO_ABS_G0_NC, llvm::AArch64II::MO_ABS_G1_NC, llvm::AArch64II::MO_ABS_G2_NC, llvm::AArch64II::MO_ABS_G3, llvm::AArch64II::MO_LO12, llvm::CodeModel::Small, llvm::AArch64ISD::WrapperLarge, and llvm::AArch64ISD::WrapperSmall.
Referenced by LowerOperation().
|
virtual |
This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.
Reimplemented from llvm::TargetLowering.
Definition at line 2838 of file AArch64ISelLowering.cpp.
References llvm::RTLIB::ADD_F128, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::RTLIB::DIV_F128, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAMEADDR, llvm::ISD::FSUB, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::JumpTable, llvm_unreachable, LowerBlockAddress(), LowerBR_CC(), LowerBRCOND(), LowerBUILD_VECTOR(), LowerF128ToCall(), LowerFP_EXTEND(), LowerFP_ROUND(), LowerFP_TO_INT(), LowerFRAMEADDR(), LowerGlobalAddressELF(), LowerGlobalTLSAddress(), LowerINT_TO_FP(), LowerJumpTable(), LowerRETURNADDR(), LowerSELECT(), LowerSELECT_CC(), LowerSETCC(), LowerVACOPY(), LowerVASTART(), LowerVECTOR_SHUFFLE(), llvm::RTLIB::MUL_F128, llvm::ISD::RETURNADDR, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SINT_TO_FP, llvm::RTLIB::SUB_F128, llvm::ISD::UINT_TO_FP, llvm::ISD::VACOPY, llvm::ISD::VASTART, and llvm::ISD::VECTOR_SHUFFLE.
|
virtual |
This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. The implementation should return the resulting token chain value.
Reimplemented from llvm::TargetLowering.
Definition at line 1220 of file AArch64ISelLowering.cpp.
References llvm::CCValAssign::AExt, llvm::CCState::AnalyzeReturn(), llvm::ISD::ANY_EXTEND, llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, CCAssignFnForNode(), llvm::CCValAssign::Full, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyToReg(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValue(), llvm::CCValAssign::isRegLoc(), llvm_unreachable, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::AArch64ISD::Ret, llvm::CCValAssign::SExt, llvm::SmallVectorTemplateCommon< T >::size(), and llvm::CCValAssign::ZExt.
| SDValue AArch64TargetLowering::LowerRETURNADDR | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2067 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::MachineFunction::addLiveIn(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getRegClassFor(), llvm::SDValue::getValueType(), llvm::MVT::i64, LowerFRAMEADDR(), and llvm::MachineFrameInfo::setReturnAddressIsTaken().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerSELECT | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2468 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::A64CC::NE, llvm::AArch64ISD::SELECT_CC, llvm::AArch64ISD::SETCC, and llvm::ISD::SETNE.
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerSELECT_CC | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2412 of file AArch64ISelLowering.cpp.
References llvm::MVT::f128, FPCCToA64CC(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getSelectableIntSetCC(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::A64CC::Invalid, llvm::EVT::isInteger(), llvm::AArch64ISD::SELECT_CC, llvm::AArch64ISD::SETCC, llvm::ISD::SETNE, and llvm::TargetLowering::softenSetCCOperands().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerSETCC | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2697 of file AArch64ISelLowering.cpp.
References llvm::MVT::f128, FPCCToA64CC(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getSelectableIntSetCC(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::A64CC::Invalid, llvm::EVT::isInteger(), llvm::EVT::isVector(), LowerVectorSETCC(), llvm::AArch64ISD::SELECT_CC, llvm::AArch64ISD::SETCC, and llvm::TargetLowering::softenSetCCOperands().
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerTLSDescCall | ( | SDValue | SymAddr, |
| SDValue | DescAddr, | ||
| SDLoc | DL, | ||
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2228 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::TargetMachine::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::TargetLoweringBase::getTargetMachine(), llvm::AArch64RegisterInfo::getTLSDescCallPreservedMask(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::AArch64ISD::GOTLoad, llvm::MVT::Other, and llvm::AArch64ISD::TLSDESCCALL.
Referenced by LowerGlobalTLSAddress().
| SDValue AArch64TargetLowering::LowerVACOPY | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2754 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), llvm::SDValue::getOperand(), and llvm::MVT::i32.
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerVASTART | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 2767 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getStore(), llvm::AArch64MachineFunctionInfo::getVariadicFPRIdx(), llvm::AArch64MachineFunctionInfo::getVariadicFPRSize(), llvm::AArch64MachineFunctionInfo::getVariadicGPRIdx(), llvm::AArch64MachineFunctionInfo::getVariadicGPRSize(), llvm::AArch64MachineFunctionInfo::getVariadicStackIdx(), llvm::MVT::i32, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::ISD::TokenFactor.
Referenced by LowerOperation().
| SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 4181 of file AArch64ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), I, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), isPermuteMask(), isREVMask(), llvm::ShuffleVectorSDNode::isSplatMask(), llvm::AArch64ISD::NEON_REV16, llvm::AArch64ISD::NEON_REV32, llvm::AArch64ISD::NEON_REV64, llvm::AArch64ISD::NEON_VDUP, llvm::AArch64ISD::NEON_VDUPLANE, llvm::AArch64ISD::NEON_VEXTRACT, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.
Referenced by isKnownShuffleVector(), and LowerOperation().
|
virtual |
This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 3771 of file AArch64ISelLowering.cpp.
References llvm::Intrinsic::aarch64_neon_vld1x2, llvm::Intrinsic::aarch64_neon_vld1x3, llvm::Intrinsic::aarch64_neon_vld1x4, llvm::Intrinsic::aarch64_neon_vst1x2, llvm::Intrinsic::aarch64_neon_vst1x3, llvm::Intrinsic::aarch64_neon_vst1x4, llvm::ISD::AND, llvm::Intrinsic::arm_neon_vld1, llvm::Intrinsic::arm_neon_vld2, llvm::Intrinsic::arm_neon_vld2lane, llvm::Intrinsic::arm_neon_vld3, llvm::Intrinsic::arm_neon_vld3lane, llvm::Intrinsic::arm_neon_vld4, llvm::Intrinsic::arm_neon_vld4lane, llvm::Intrinsic::arm_neon_vst1, llvm::Intrinsic::arm_neon_vst2, llvm::Intrinsic::arm_neon_vst2lane, llvm::Intrinsic::arm_neon_vst3, llvm::Intrinsic::arm_neon_vst3lane, llvm::Intrinsic::arm_neon_vst4, llvm::Intrinsic::arm_neon_vst4lane, CombineBaseUpdate(), CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::AArch64ISD::NEON_LD2DUP, llvm::AArch64ISD::NEON_LD3DUP, llvm::AArch64ISD::NEON_LD4DUP, llvm::AArch64ISD::NEON_VDUPLANE, llvm::ISD::OR, PerformANDCombine(), PerformIntrinsicCombine(), PerformORCombine(), PerformShiftCombine(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
| void AArch64TargetLowering::SaveVarArgRegisters | ( | CCState & | CCInfo, |
| SelectionDAG & | DAG, | ||
| SDLoc | DL, | ||
| SDValue & | Chain | ||
| ) | const |
Definition at line 1032 of file AArch64ISelLowering.cpp.
References AArch64ArgRegs, AArch64FPRArgRegs, llvm::ISD::ADD, llvm::MachineFunction::addLiveIn(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::CreateStackObject(), llvm::MVT::f128, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::CCState::getFirstUnallocated(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::CCState::getNextStackOffset(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::MachinePointerInfo::getStack(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::AArch64Subtarget::hasFPARMv8(), llvm::MVT::i64, NumArgRegs, NumFPRArgRegs, llvm::MVT::Other, llvm::AArch64MachineFunctionInfo::setVariadicFPRIdx(), llvm::AArch64MachineFunctionInfo::setVariadicFPRSize(), llvm::AArch64MachineFunctionInfo::setVariadicGPRIdx(), llvm::AArch64MachineFunctionInfo::setVariadicGPRSize(), llvm::AArch64MachineFunctionInfo::setVariadicStackIdx(), llvm::SPII::Store, and llvm::ISD::TokenFactor.
Referenced by LowerFormalArguments().
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Public Member Functions inherited from