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ARMISelLowering.cpp File Reference
#include "ARMISelLowering.h"
#include "ARM.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMSubtarget.h"
#include "ARMTargetMachine.h"
#include "ARMTargetObjectFile.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Type.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include <utility>
#include "ARMGenCallingConv.inc"
Include dependency graph for ARMISelLowering.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "arm-isel"
 

Typedefs

typedef std::pair< unsigned,
const TargetRegisterClass * > 		RCPair
 

Functions

 STATISTIC (NumTailCalls,"Number of tail calls")
 
 STATISTIC (NumMovwMovt,"Number of GAs materialized with movw + movt")
 
 STATISTIC (NumLoopByVals,"Number of loops generated for byval arguments")
 
static TargetLoweringObjectFile * createTLOF (TargetMachine &TM)
 
static void getExclusiveOperation (unsigned Size, AtomicOrdering Ord, bool isThumb2, unsigned &LdrOpc, unsigned &StrOpc)
 
static ARMCC::CondCodes IntCCToARMCC (ISD::CondCode CC)
 IntCCToARMCC - Convert a DAG integer condition code to an ARM CC. More...
 
static void FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
 FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. More...
 
static bool MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
 
static SDValue LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, SDLoc DL, SelectionDAG &DAG)
 
static SDValue LowerConstantPool (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerVASTART (SDValue Op, SelectionDAG &DAG)
 
static bool isFloatingPointZero (SDValue Op)
 isFloatingPointZero - Return true if this is +0.0. More...
 
static ISD::CondCode getInverseCCForVSEL (ISD::CondCode CC)
 
static void checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)
 
static bool canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
 
static SDValue bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG)
 
static void expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)
 
static SDValue LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerFP_TO_INT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerINT_TO_FP (SDValue Op, SelectionDAG &DAG)
 
static SDValue ExpandBITCAST (SDNode *N, SelectionDAG &DAG)
 
static SDValue getZeroVector (EVT VT, SelectionDAG &DAG, SDLoc dl)
 
static SDValue LowerCTTZ (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue getCTPOP16BitCounts (SDNode *N, SelectionDAG &DAG)
 
static SDValue lowerCTPOP16BitElements (SDNode *N, SelectionDAG &DAG)
 
static SDValue lowerCTPOP32BitElements (SDNode *N, SelectionDAG &DAG)
 
static SDValue LowerCTPOP (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue Expand64BitShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerVSETCC (SDValue Op, SelectionDAG &DAG)
 
static SDValue isNEONModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, EVT &VT, bool is128Bits, NEONModImmType type)
 
static bool isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
 
static bool isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)
 
static bool isVREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize)
 
static bool isVTBLMask (ArrayRef< int > M, EVT VT)
 
static bool isVTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isReverseMask (ArrayRef< int > M, EVT VT)
 
static SDValue IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, SDLoc dl)
 
static SDValue GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, SDLoc dl)
 
static SDValue LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
 
static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerINSERT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG)
 
static bool isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
 
static bool isSignExtended (SDNode *N, SelectionDAG &DAG)
 
static bool isZeroExtended (SDNode *N, SelectionDAG &DAG)
 
static EVT getExtensionTo64Bits (const EVT &OrigVT)
 
static SDValue AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
 
static SDValue SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG)
 
static SDValue SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG)
 
static bool isAddSubSExt (SDNode *N, SelectionDAG &DAG)
 
static bool isAddSubZExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue LowerMUL (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerSDIV_v4i8 (SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG)
 
static SDValue LowerSDIV_v4i16 (SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG)
 
static SDValue LowerSDIV (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerUDIV (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG)
 
static void ReplaceATOMIC_OP_64 (SDNode *Node, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
 
static void ReplaceREADCYCLECOUNTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static MachineBasicBlock * OtherSucc (MachineBasicBlock *MBB, MachineBasicBlock *Succ)
 
static unsigned getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2)
 
static unsigned getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2)
 
static void emitPostLd (MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
 
static void emitPostSt (MachineBasicBlock *BB, MachineInstr *Pos, const TargetInstrInfo *TII, DebugLoc dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
 
static bool isZeroOrAllOnes (SDValue N, bool AllOnes)
 
static bool isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
 
static SDValue combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)
 
static SDValue combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue AddCombineToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue findMUL_LOHI (SDValue V)
 
static SDValue AddCombineTo64bitMLAL (SDNode *AddcNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformADDCCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformADDCombineWithOperands (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformSUBCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformORCombine - Target-specific dag combine xforms for ISD::OR. More...
 
static SDValue PerformXORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformBFICombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVMOVRRDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue PerformSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static bool hasNormalLoadOperand (SDNode *N)
 
static SDValue PerformBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 Target-specific dag combine xforms for ARMISD::BUILD_VECTOR. More...
 
static SDValue PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static bool CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVDUPLANECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static bool isConstVecPow2 (SDValue ConstVec, bool isSigned, uint64_t &C)
 
static SDValue PerformVCVTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformVDIVCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static bool getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
 
static bool isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
 
static bool isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
 
static SDValue PerformIntrinsicCombine (SDNode *N, SelectionDAG &DAG)
 PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. More...
 
static SDValue PerformShiftCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue PerformExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue PerformSELECT_CCCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static bool memOpAlign (unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck)
 
static bool isLegalT1AddressImmediate (int64_t V, EVT VT)
 
static bool isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
 
static bool isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
 
static bool getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
 
static bool getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
 

Variables

static cl::opt< bool > EnableARMTailCalls ("arm-tail-calls", cl::Hidden, cl::desc("Generate tail calls (TEMPORARY OPTION)."), cl::init(false))
 
cl::opt< bool > EnableARMLongCalls ("arm-long-calls", cl::Hidden, cl::desc("Generate calls via indirect call instructions"), cl::init(false))
 
static cl::opt< bool > ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
 
static const uint16_t GPRArgRegs []
 

Macro Definition Documentation

#define DEBUG_TYPE   "arm-isel"

Definition at line 15 of file ARMISelLowering.cpp.

Typedef Documentation

typedef std::pair<unsigned, const TargetRegisterClass*> RCPair

Definition at line 10845 of file ARMISelLowering.cpp.

Function Documentation

static SDValue AddCombineTo64bitMLAL ( SDNode *  AddcNode,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 8296 of file ARMISelLowering.cpp.

References llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLowering::DAGCombinerInfo::DAG, findMUL_LOHI(), llvm::SDNode::getGluedUser(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::ARMISD::SMLAL, llvm::ISD::SMUL_LOHI, llvm::ARMISD::UMLAL, and llvm::ISD::UMUL_LOHI.

Referenced by PerformADDCCombine().

static SDValue AddCombineToVPADDL ( SDNode *  N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 8202 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vpaddls, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i16, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MVT::SimpleTy, llvm::SmallVectorTemplateCommon< T >::size(), and llvm::ISD::TRUNCATE.

Referenced by PerformADDCombineWithOperands().

static SDValue AddRequiredExtensionForVMULL ( SDValue  N,
SelectionDAG &  DAG,
const EVT &  OrigTy,
const EVT &  ExtTy,
unsigned  ExtOpcode 
)
static

AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits. We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.

Definition at line 5587 of file ARMISelLowering.cpp.

References getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), and llvm::EVT::is128BitVector().

Referenced by SkipExtensionForVMULL().

static SDValue bitcastf32Toi32 ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 3442 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::MVT::i32, isFloatingPointZero(), and llvm_unreachable.

static bool canChangeToInt ( SDValue  Op,
bool &  SeenZero,
const ARMSubtarget *  Subtarget 
)
static

canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.

Definition at line 3421 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), isFloatingPointZero(), llvm::ARMSubtarget::isFPBrccSlow(), and llvm::ISD::isNormalLoad().

static void checkVSELConstraints ( ISD::CondCode  CC,
ARMCC::CondCodes &  CondCode,
bool &  swpCmpOps,
bool &  swpVselOps 
)
static

Definition at line 3285 of file ARMISelLowering.cpp.

References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ARMCC::VS.

static SDValue CombineBaseUpdate ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and NEON load/store intrinsics to merge base address updates.

Definition at line 9327 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::Intrinsic::arm_neon_vld1, llvm::Intrinsic::arm_neon_vld2, llvm::Intrinsic::arm_neon_vld2lane, llvm::Intrinsic::arm_neon_vld3, llvm::Intrinsic::arm_neon_vld3lane, llvm::Intrinsic::arm_neon_vld4, llvm::Intrinsic::arm_neon_vld4lane, llvm::Intrinsic::arm_neon_vst1, llvm::Intrinsic::arm_neon_vst2, llvm::Intrinsic::arm_neon_vst2lane, llvm::Intrinsic::arm_neon_vst3, llvm::Intrinsic::arm_neon_vst3lane, llvm::Intrinsic::arm_neon_vst4, llvm::Intrinsic::arm_neon_vst4lane, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorTemplateCommon< T >::data(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::SDNode::isPredecessorOf(), llvm_unreachable, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, and llvm::ARMISD::VST4LN_UPD.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue combineSelectAndUse ( SDNode *  N,
SDValue  Slct,
SDValue  OtherOp,
TargetLowering::DAGCombinerInfo &  DCI,
bool  AllOnes = false 
)
static

Definition at line 8157 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), isConditionalZeroOrAllOnes(), llvm::ISD::SELECT, and std::swap().

Referenced by combineSelectAndUseCommutative(), PerformADDCombineWithOperands(), and PerformSUBCombine().

static SDValue combineSelectAndUseCommutative ( SDNode *  N,
bool  AllOnes,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

Definition at line 8183 of file ARMISelLowering.cpp.

References combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), and llvm::SDNode::hasOneUse().

Referenced by PerformANDCombine(), PerformORCombine(), and PerformXORCombine().

static bool CombineVLDDUP ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs. If so, combine them to a vldN-dup operation and return true.

Definition at line 9461 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vld2lane, llvm::Intrinsic::arm_neon_vld3lane, llvm::Intrinsic::arm_neon_vld4lane, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is64BitVector(), llvm::MVT::Other, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ARMISD::VDUPLANE, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, and llvm::ARMISD::VLD4DUP.

Referenced by PerformVDUPLANECombine().

static TargetLoweringObjectFile* createTLOF ( TargetMachine &  TM)
static

Definition at line 163 of file ARMISelLowering.cpp.

References llvm::TargetMachine::getSubtarget(), and llvm::ARMSubtarget::isTargetDarwin().

static void emitPostLd ( MachineBasicBlock *  BB,
MachineInstr *  Pos,
const TargetInstrInfo *  TII,
DebugLoc  dl,
unsigned  LdSize,
unsigned  Data,
unsigned  AddrIn,
unsigned  AddrOut,
bool  IsThumb1,
bool  IsThumb2 
)
static

Emit a post-increment load operation with given size. The instructions will be added to BB at Pos.

Definition at line 7313 of file ARMISelLowering.cpp.

References llvm::AddDefaultPred(), llvm::AddDefaultT1CC(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::MCInstrInfo::get(), and getLdOpcode().

static void emitPostSt ( MachineBasicBlock *  BB,
MachineInstr *  Pos,
const TargetInstrInfo *  TII,
DebugLoc  dl,
unsigned  StSize,
unsigned  Data,
unsigned  AddrIn,
unsigned  AddrOut,
bool  IsThumb1,
bool  IsThumb2 
)
static

Emit a post-increment store operation with given size. The instructions will be added to BB at Pos.

Definition at line 7345 of file ARMISelLowering.cpp.

References llvm::AddDefaultPred(), llvm::AddDefaultT1CC(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MCInstrInfo::get(), and getStOpcode().

static SDValue Expand64BitShift ( SDNode *  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST 
)
static

Definition at line 4131 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::HexagonISD::Hi, llvm::MVT::i64, llvm::ARMSubtarget::isThumb1Only(), llvm::ARMISD::RRX, llvm::ISD::SRA, llvm::ARMISD::SRA_FLAG, llvm::ISD::SRL, and llvm::ARMISD::SRL_FLAG.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

static SDValue ExpandBITCAST ( SDNode *  N,
SelectionDAG &  DAG 
)
static

ExpandBITCAST - If the target supports VFP, this function is called to expand a bit convert where either the source or destination type is i64 to use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 operand type is illegal (e.g., v2f32 for a target that doesn't support vectors), since the legalizer won't know what to do with that.

Definition at line 3840 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_PAIR, llvm::ISD::EXTRACT_ELEMENT, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i64, llvm::TargetLoweringBase::isTypeLegal(), llvm::ARMISD::VMOVDRR, and llvm::ARMISD::VMOVRRD.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

static void expandf64Toi32 ( SDValue  Op,
SelectionDAG &  DAG,
SDValue &  RetVal1,
SDValue &  RetVal2 
)
static

Definition at line 3455 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, isFloatingPointZero(), llvm_unreachable, and llvm::MinAlign().

static SDValue findMUL_LOHI ( SDValue  V)
static

Definition at line 8289 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.

Referenced by AddCombineTo64bitMLAL().

static void FPCCToARMCC ( ISD::CondCode  CC,
ARMCC::CondCodes &  CondCode,
ARMCC::CondCodes &  CondCode2 
)
static

FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.

Definition at line 1235 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ARMCC::VC, and llvm::ARMCC::VS.

static SDValue GeneratePerfectShuffle ( unsigned  PFEntry,
SDValue  LHS,
SDValue  RHS,
SelectionDAG &  DAG,
SDLoc  dl 
)
static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 5183 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i8, llvm_unreachable, PerfectShuffleTable, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, llvm::ARMISD::VREV64, llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

Referenced by LowerVECTOR_SHUFFLE().

static bool getARMIndexedAddressParts ( SDNode *  Ptr,
EVT  VT,
bool  isSEXTLoad,
SDValue &  Base,
SDValue &  Offset,
bool &  isInc,
SelectionDAG &  DAG 
)
static

Definition at line 10543 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ARM_AM::getShiftOpcForNode(), llvm::SDNode::getValueType(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, llvm::ARM_AM::no_shift, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

static SDValue getCTPOP16BitCounts ( SDNode *  N,
SelectionDAG &  DAG 
)
static

getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count for each 16-bit element from operand, repeated. The basic idea is to leverage vcnt to get the 8-bit counts, gather and add the results.

Trace for v4i16: input = [v0 v1 v2 v3 ] (vi 16-bit element) cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element) vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi) vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6] [b0 b1 b2 b3 b4 b5 b6 b7] +[b1 b0 b3 b2 b5 b4 b7 b6] N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0, vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)

Definition at line 4001 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::CTPOP, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::is64BitVector(), llvm::MVT::v16i8, llvm::MVT::v8i8, llvm::ARMISD::VREV16, and llvm::ARMISD::VUZP.

Referenced by lowerCTPOP16BitElements().

static void getExclusiveOperation ( unsigned  Size,
AtomicOrdering  Ord,
bool  isThumb2,
unsigned &  LdrOpc,
unsigned &  StrOpc 
)
static

Definition at line 923 of file ARMISelLowering.cpp.

References llvm::Acquire, llvm::AcquireRelease, llvm::isPowerOf2_32(), llvm::Log2_32(), llvm::Release, and llvm::SequentiallyConsistent.

static EVT getExtensionTo64Bits ( const EVT &  OrigVT)
static

Definition at line 5567 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4i16, and llvm::MVT::v4i8.

Referenced by AddRequiredExtensionForVMULL(), and SkipLoadExtensionForVMULL().

static ISD::CondCode getInverseCCForVSEL ( ISD::CondCode  CC)
static

Definition at line 3279 of file ARMISelLowering.cpp.

References llvm::ISD::getSetCCSwappedOperands(), llvm::ISD::SETEQ, and llvm::ISD::SETNE.

static unsigned getLdOpcode ( unsigned  LdSize,
bool  IsThumb1,
bool  IsThumb2 
)
static

Return the load opcode for a given load size. If load size >= 8, neon opcode will be returned.

Definition at line 7275 of file ARMISelLowering.cpp.

Referenced by emitPostLd().

static unsigned getStOpcode ( unsigned  StSize,
bool  IsThumb1,
bool  IsThumb2 
)
static

Return the store opcode for a given store size. If store size >= 8, neon opcode will be returned.

Definition at line 7294 of file ARMISelLowering.cpp.

Referenced by emitPostSt().

static bool getT2IndexedAddressParts ( SDNode *  Ptr,
EVT  VT,
bool  isSEXTLoad,
SDValue &  Base,
SDValue &  Offset,
bool &  isInc,
SelectionDAG &  DAG 
)
static

Definition at line 10602 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

static bool getVShiftImm ( SDValue  Op,
unsigned  ElementBits,
int64_t &  Cnt 
)
static

Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 9702 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::BuildVectorSDNode::isConstantSplat().

Referenced by isVShiftLImm(), and isVShiftRImm().

static SDValue getZeroVector ( EVT  VT,
SelectionDAG &  DAG,
SDLoc  dl 
)
static

getZeroVector - Returns a vector of specified type with all zero elements. Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.

Definition at line 3879 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::is128BitVector(), llvm::EVT::isVector(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ARMISD::VMOVIMM.

Referenced by LowerShift().

static bool hasNormalLoadOperand ( SDNode *  N)
static

hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads. If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.

Definition at line 9110 of file ARMISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and llvm::ISD::isNormalLoad().

Referenced by PerformBUILD_VECTORCombine().

static ARMCC::CondCodes IntCCToARMCC ( ISD::CondCode  CC)
static

IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.

Definition at line 1218 of file ARMISelLowering.cpp.

References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

static bool isAddSubSExt ( SDNode *  N,
SelectionDAG &  DAG 
)
static

Definition at line 5672 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isSignExtended(), and llvm::ISD::SUB.

Referenced by LowerMUL().

static bool isAddSubZExt ( SDNode *  N,
SelectionDAG &  DAG 
)
static

Definition at line 5683 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isZeroExtended(), and llvm::ISD::SUB.

Referenced by LowerMUL().

static bool isConditionalZeroOrAllOnes ( SDNode *  N,
bool  AllOnes,
SDValue &  CC,
bool &  Invert,
SDValue &  OtherOp,
SelectionDAG &  DAG 
)
static

Definition at line 8085 of file ARMISelLowering.cpp.

References llvm::APInt::getAllOnesValue(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i1, isZeroOrAllOnes(), llvm::ISD::SELECT, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineSelectAndUse().

static bool isConstVecPow2 ( SDValue  ConstVec,
bool  isSigned,
uint64_t &  C 
)
static

Definition at line 9572 of file ARMISelLowering.cpp.

References llvm::APFloat::convertToInteger(), llvm::dyn_cast(), llvm::SDValue::getOperand(), llvm::ConstantFPSDNode::getValueAPF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), I, llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::APFloat::opOK, and llvm::APFloat::rmTowardZero.

Referenced by PerformVCVTCombine(), and PerformVDIVCombine().

static bool isExtendedBUILD_VECTOR ( SDNode *  N,
SelectionDAG &  DAG,
bool  isSigned 
)
static

isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.

Definition at line 5496 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::isBigEndian(), llvm::isIntN(), llvm::isUIntN(), llvm::MVT::v2i64, and llvm::MVT::v4i32.

Referenced by isSignExtended(), and isZeroExtended().

static bool isFloatingPointZero ( SDValue  Op)
static

isFloatingPointZero - Return true if this is +0.0.

Definition at line 3119 of file ARMISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), and llvm::ARMISD::Wrapper.

Referenced by bitcastf32Toi32(), canChangeToInt(), and expandf64Toi32().

static bool isLegalAddressImmediate ( int64_t  V,
EVT  VT,
const ARMSubtarget *  Subtarget 
)
static

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

Definition at line 10383 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().

static bool isLegalT1AddressImmediate ( int64_t  V,
EVT  VT 
)
static

Definition at line 10323 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

static bool isLegalT2AddressImmediate ( int64_t  V,
EVT  VT,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 10350 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

static SDValue isNEONModifiedImm ( uint64_t  SplatBits,
uint64_t  SplatUndef,
unsigned  SplatBitSize,
SelectionDAG &  DAG,
EVT &  VT,
bool  is128Bits,
NEONModImmType  type 
)
static

isNEONModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON instruction with a "modified immediate" operand (e.g., VMOV). If so, return the encoded value.

Definition at line 4303 of file ARMISelLowering.cpp.

References llvm::ARM_AM::createNEONModImm(), llvm::SelectionDAG::getTargetConstant(), llvm::X86II::ImmMask, llvm_unreachable, llvm::OtherModImm, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::VMOVModImm.

Referenced by PerformANDCombine(), and PerformORCombine().

static bool isReverseMask ( ArrayRef< int >  M,
EVT  VT 
)
static
Returns
true if this is a reverse operation on an vector.

Definition at line 4747 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and llvm::ArrayRef< T >::size().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isSignExtended ( SDNode *  N,
SelectionDAG &  DAG 
)
static

isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.

Definition at line 5549 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), and llvm::ISD::SIGN_EXTEND.

Referenced by isAddSubSExt(), and LowerMUL().

static SDValue IsSingleInstrConstant ( SDValue  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST,
SDLoc  dl 
)
static

Definition at line 4764 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getSOImmVal(), llvm::ARMSubtarget::isThumb1Only(), and N.

static bool isSingletonVEXTMask ( ArrayRef< int >  M,
EVT  VT,
unsigned &  Imm 
)
static

Definition at line 4518 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by LowerVECTOR_SHUFFLE().

static bool isVEXTMask ( ArrayRef< int >  M,
EVT  VT,
bool &  ReverseVEXT,
unsigned &  Imm 
)
static

Definition at line 4547 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVREVMask ( ArrayRef< int >  M,
EVT  VT,
unsigned  BlockSize 
)
static

isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize. (The order of the elements within each block of the vector is reversed.)

Definition at line 4586 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), and llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVShiftLImm ( SDValue  Op,
EVT  VT,
bool  isLong,
int64_t &  Cnt 
)
static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 9722 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by PerformIntrinsicCombine(), and PerformShiftCombine().

static bool isVShiftRImm ( SDValue  Op,
EVT  VT,
bool  isNarrow,
bool  isIntrinsic,
int64_t &  Cnt 
)
static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 9736 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by PerformIntrinsicCombine(), and PerformShiftCombine().

static bool isVTBLMask ( ArrayRef< int >  M,
EVT  VT 
)
static

Definition at line 4612 of file ARMISelLowering.cpp.

References llvm::ArrayRef< T >::size(), and llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().

static bool isVTRN_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned &  WhichResult 
)
static

isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 4637 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), and llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVTRNMask ( ArrayRef< int >  M,
EVT  VT,
unsigned &  WhichResult 
)
static

Definition at line 4619 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), and llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVUZP_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned &  WhichResult 
)
static

isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 4675 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::is64BitVector().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVUZPMask ( ArrayRef< int >  M,
EVT  VT,
unsigned &  WhichResult 
)
static

Definition at line 4652 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::is64BitVector().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVZIP_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned &  WhichResult 
)
static

isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 4724 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::is64BitVector().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVZIPMask ( ArrayRef< int >  M,
EVT  VT,
unsigned &  WhichResult 
)
static

Definition at line 4699 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::is64BitVector().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isZeroExtended ( SDNode *  N,
SelectionDAG &  DAG 
)
static

isZeroExtended - Check if a node is a vector value that is zero-extended or a constant BUILD_VECTOR with zero-extended elements.

Definition at line 5559 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), and llvm::ISD::ZERO_EXTEND.

Referenced by isAddSubZExt(), and LowerMUL().

static bool isZeroOrAllOnes ( SDValue  N,
bool  AllOnes 
)
inlinestatic

Definition at line 8066 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::ConstantSDNode::isAllOnesValue(), llvm::ConstantSDNode::isNullValue(), and N.

Referenced by isConditionalZeroOrAllOnes().

static SDValue LowerADDC_ADDE_SUBC_SUBE ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5944 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ISD::ADDC, llvm::ARMISD::ADDE, llvm::ISD::ADDE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm_unreachable, llvm::ARMISD::SUBC, llvm::ISD::SUBC, llvm::ARMISD::SUBE, and llvm::ISD::SUBE.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerATOMIC_FENCE ( SDValue  Op,
SelectionDAG &  DAG,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 2678 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_dmb, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::ARMSubtarget::hasDataBarrier(), llvm::ARMSubtarget::hasV6Ops(), llvm::MVT::i32, llvm::ISD::INTRINSIC_VOID, llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, llvm::ARMSubtarget::isMClass(), llvm::ARMSubtarget::isSwift(), llvm::ARMSubtarget::isThumb(), llvm::ARMISD::MEMBARRIER_MCR, llvm::MVT::Other, llvm::Release, and llvm::ARM_MB::SY.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerAtomicLoadStore ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 6029 of file ARMISelLowering.cpp.

References llvm::Monotonic.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerCONCAT_VECTORS ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5473 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f64, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::is128BitVector(), llvm::ISD::UNDEF, and llvm::MVT::v2f64.

Referenced by llvm::ARMTargetLowering::LowerOperation(), LowerSDIV(), and LowerUDIV().

static SDValue LowerConstantPool ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 2328 of file ARMISelLowering.cpp.

References llvm::ConstantPoolSDNode::getAlignment(), llvm::ConstantPoolSDNode::getConstVal(), llvm::ConstantPoolSDNode::getMachineCPVal(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ConstantPoolSDNode::isMachineConstantPoolEntry(), and llvm::ARMISD::Wrapper.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerCTPOP ( SDNode *  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST 
)
static

Definition at line 4081 of file ARMISelLowering.cpp.

References llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i32, lowerCTPOP16BitElements(), lowerCTPOP32BitElements(), llvm::MVT::v2i32, llvm::MVT::v4i16, llvm::MVT::v4i32, and llvm::MVT::v8i16.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue lowerCTPOP16BitElements ( SDNode *  N,
SelectionDAG &  DAG 
)
static

lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the bit-count for each 16-bit element from the operand. We need slightly different sequencing for v4i16 and v8i16 to stay within NEON's available 64/128-bit registers.

Trace for v4i16: input = [v0 v1 v2 v3 ] (vi 16-bit element) v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi) v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ] v4i16:Extracted = [k0 k1 k2 k3 ]

Definition at line 4023 of file ARMISelLowering.cpp.

References llvm::ISD::EXTRACT_SUBVECTOR, getCTPOP16BitCounts(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getValueType(), llvm::EVT::is64BitVector(), llvm::MVT::v4i16, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerCTPOP(), and lowerCTPOP32BitElements().

static SDValue lowerCTPOP32BitElements ( SDNode *  N,
SelectionDAG &  DAG 
)
static

lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the bit-count for each 32-bit element from the operand. The idea here is to split the vector into 16-bit elements, leverage the 16-bit count routine, and then combine the results.

Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged): input = [v0 v1 ] (vi: 32-bit elements) Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1]) Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi) vrev: N0 = [k1 k0 k3 k2 ] [k0 k1 k2 k3 ] N1 =+[k1 k0 k3 k2 ] [k0 k2 k1 k3 ] N2 =+[k1 k3 k0 k2 ] [k0 k2 k1 k3 ] Extended =+[k1 k3 k0 k2 ] [k0 k2 ] Extracted=+[k1 k3 ]

Definition at line 4058 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::MCID::Bitcast, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::is64BitVector(), lowerCTPOP16BitElements(), llvm::MVT::v2i32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ARMISD::VREV32, llvm::ARMISD::VUZP, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerCTPOP().

static SDValue LowerCTTZ ( SDNode *  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST 
)
static

Definition at line 3976 of file ARMISelLowering.cpp.

References llvm::ISD::CTLZ, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasV6T2Ops(), and llvm::ARMISD::RBIT.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerEXTRACT_VECTOR_ELT ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5457 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), and llvm::ARMISD::VGETLANEu.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerFP_TO_INT ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 3639 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ARMISD::FTOSI, llvm::ARMISD::FTOUI, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), llvm_unreachable, and LowerVectorFP_TO_INT().

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerINSERT_VECTOR_ELT ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5448 of file ARMISelLowering.cpp.

References llvm::SDValue::getOperand().

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerINT_TO_FP ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 3693 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), llvm_unreachable, LowerVectorINT_TO_FP(), llvm::ISD::SINT_TO_FP, llvm::ARMISD::SITOF, llvm::ISD::UINT_TO_FP, and llvm::ARMISD::UITOF.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerInterruptReturn ( SmallVectorImpl< SDValue > &  RetOps,
SDLoc  DL,
SelectionDAG &  DAG 
)
static

Definition at line 2112 of file ARMISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorTemplateCommon< T >::data(), F(), llvm::SelectionDAG::getConstant(), llvm::Function::getFnAttribute(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::Attribute::getValueAsString(), llvm::MVT::i32, llvm::SmallVectorImpl< T >::insert(), llvm::ARMISD::INTRET_FLAG, llvm::MVT::Other, llvm::report_fatal_error(), and llvm::SmallVectorTemplateCommon< T >::size().

static SDValue LowerMUL ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5694 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isAddSubSExt(), isAddSubZExt(), llvm::EVT::isInteger(), isSignExtended(), isZeroExtended(), SkipExtensionForVMULL(), std::swap(), llvm::MVT::v2i64, llvm::ARMISD::VMULLs, and llvm::ARMISD::VMULLu.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerPREFETCH ( SDValue  Op,
SelectionDAG &  DAG,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 2710 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::ARMSubtarget::hasMPExtension(), llvm::ARMSubtarget::hasV5TEOps(), llvm::ARMSubtarget::hasV7Ops(), llvm::MVT::i32, llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::MVT::Other, and llvm::ARMISD::PRELOAD.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5282 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::v16i8, llvm::MVT::v8i16, llvm::ARMISD::VEXT, and llvm::ARMISD::VREV64.

Referenced by LowerVECTOR_SHUFFLE().

static SDValue LowerSDIV ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5835 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::MVT::v4i16, llvm::MVT::v8i16, and llvm::MVT::v8i8.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerSDIV_v4i16 ( SDValue  N0,
SDValue  N1,
SDLoc  dl,
SelectionDAG &  DAG 
)
static

Definition at line 5799 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::Intrinsic::arm_neon_vrecpe, llvm::Intrinsic::arm_neon_vrecps, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, and llvm::MVT::v4i32.

Referenced by LowerSDIV(), and LowerUDIV().

static SDValue LowerSDIV_v4i8 ( SDValue  X,
SDValue  Y,
SDLoc  dl,
SelectionDAG &  DAG 
)
static

Definition at line 5770 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::Intrinsic::arm_neon_vrecpe, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::X, and Y.

Referenced by LowerSDIV().

static SDValue LowerShift ( SDNode *  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST 
)
static

Definition at line 4096 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vshifts, llvm::Intrinsic::arm_neon_vshiftu, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), getZeroVector(), llvm::ARMSubtarget::hasNEON(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isVector(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerUDIV ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5870 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::Intrinsic::arm_neon_vqmovnsu, llvm::Intrinsic::arm_neon_vrecpe, llvm::Intrinsic::arm_neon_vrecps, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerVASTART ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 2737 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ARMFunctionInfo::getVarArgsFrameIndex().

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 5299 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplatMask(), isVEXTMask(), isVREVMask(), isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerVECTOR_SHUFFLEv8i8(), PerfectShuffleTable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, std::swap(), llvm::ISD::UNDEF, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, llvm::ARMISD::VREV64, llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerVECTOR_SHUFFLEv8i8 ( SDValue  Op,
ArrayRef< int >  ShuffleMask,
SelectionDAG &  DAG 
)
static

Definition at line 5259 of file ARMISelLowering.cpp.

References llvm::ArrayRef< T >::begin(), llvm::ISD::BUILD_VECTOR, llvm::ArrayRef< T >::end(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), I, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8i8, llvm::ARMISD::VTBL1, and llvm::ARMISD::VTBL2.

Referenced by LowerVECTOR_SHUFFLE().

static SDValue LowerVectorFP_TO_INT ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 3620 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::ISD::TRUNCATE, llvm::SelectionDAG::UnrollVectorOp(), llvm::MVT::v4f32, llvm::MVT::v4i16, and llvm::MVT::v4i32.

Referenced by LowerFP_TO_INT().

static SDValue LowerVectorINT_TO_FP ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 3660 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SelectionDAG::UnrollVectorOp(), llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerINT_TO_FP().

static SDValue LowerVSETCC ( SDValue  Op,
SelectionDAG &  DAG 
)
static

Definition at line 4169 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isFloatingPoint(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, std::swap(), llvm::ARMISD::VCEQ, llvm::ARMISD::VCEQZ, llvm::ARMISD::VCGE, llvm::ARMISD::VCGEU, llvm::ARMISD::VCGEZ, llvm::ARMISD::VCGT, llvm::ARMISD::VCGTU, llvm::ARMISD::VCGTZ, llvm::ARMISD::VCLEZ, llvm::ARMISD::VCLTZ, and llvm::ARMISD::VTST.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static bool MatchingStackOffset ( SDValue  Arg,
unsigned  Offset,
ISD::ArgFlagsTy  Flags,
MachineFrameInfo *  MFI,
const MachineRegisterInfo *  MRI,
const TargetInstrInfo *  TII 
)
static

MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.

Definition at line 1913 of file ARMISelLowering.cpp.

References llvm::ISD::CopyFromReg, llvm::tgtok::Def, llvm::dyn_cast(), llvm::FrameIndexSDNode::getIndex(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getReg(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::TargetInstrInfo::isLoadFromStackSlot(), and llvm::TargetRegisterInfo::isVirtualRegister().

static bool memOpAlign ( unsigned  DstAlign,
unsigned  SrcAlign,
unsigned  AlignCheck 
)
static

Definition at line 10247 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::getOptimalMemOpType().

static MachineBasicBlock* OtherSucc ( MachineBasicBlock *  MBB,
MachineBasicBlock *  Succ 
)
static

Definition at line 7265 of file ARMISelLowering.cpp.

References I, llvm_unreachable, llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

static SDValue PerformADDCCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

PerformADDCCombine - Target-specific dag combine transform from ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.

Definition at line 8432 of file ARMISelLowering.cpp.

References AddCombineTo64bitMLAL().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformADDCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 8463 of file ARMISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), and PerformADDCombineWithOperands().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformADDCombineWithOperands ( SDNode *  N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1. This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 8444 of file ARMISelLowering.cpp.

References AddCombineToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), and llvm::SDNode::hasOneUse().

Referenced by PerformADDCombine().

static SDValue PerformANDCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 8624 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::APInt::getZExtValue(), llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), isNEONModifiedImm(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::OtherModImm, and llvm::ARMISD::VBICIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformARMBUILD_VECTORCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.

Definition at line 9156 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDNode::hasOneUse(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), llvm::ISD::UNDEF, and llvm::SDNode::use_begin().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformBFICombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff the bits being cleared by the AND are not demanded by the BFI.

Definition at line 8886 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ARMISD::BFI, llvm::countLeadingZeros(), llvm::countTrailingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and llvm::ConstantSDNode::getZExtValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformBUILD_VECTORCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.

Definition at line 9122 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorTemplateCommon< T >::data(), llvm::MVT::f64, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), hasNormalLoadOperand(), llvm::MVT::i64, PerformVMOVDRRCombine(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformExtendCombine ( SDNode *  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST 
)
static

PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.

Definition at line 9960 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i16, llvm::MVT::i8, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ARMISD::VGETLANEs, llvm::ARMISD::VGETLANEu, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformInsertEltCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.

Definition at line 9248 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, and llvm::ISD::isNormalLoad().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformIntrinsicCombine ( SDNode *  N,
SelectionDAG &  DAG 
)
static

PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.

Definition at line 9748 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vqrshiftns, llvm::Intrinsic::arm_neon_vqrshiftnsu, llvm::Intrinsic::arm_neon_vqrshiftnu, llvm::Intrinsic::arm_neon_vqrshifts, llvm::Intrinsic::arm_neon_vqrshiftu, llvm::Intrinsic::arm_neon_vqshiftns, llvm::Intrinsic::arm_neon_vqshiftnsu, llvm::Intrinsic::arm_neon_vqshiftnu, llvm::Intrinsic::arm_neon_vqshifts, llvm::Intrinsic::arm_neon_vqshiftsu, llvm::Intrinsic::arm_neon_vqshiftu, llvm::Intrinsic::arm_neon_vrshiftn, llvm::Intrinsic::arm_neon_vrshifts, llvm::Intrinsic::arm_neon_vrshiftu, llvm::Intrinsic::arm_neon_vshiftins, llvm::Intrinsic::arm_neon_vshiftls, llvm::Intrinsic::arm_neon_vshiftlu, llvm::Intrinsic::arm_neon_vshiftn, llvm::Intrinsic::arm_neon_vshifts, llvm::Intrinsic::arm_neon_vshiftu, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, llvm::ARMISD::VQRSHRNs, llvm::ARMISD::VQRSHRNsu, llvm::ARMISD::VQRSHRNu, llvm::ARMISD::VQSHLs, llvm::ARMISD::VQSHLsu, llvm::ARMISD::VQSHLu, llvm::ARMISD::VQSHRNs, llvm::ARMISD::VQSHRNsu, llvm::ARMISD::VQSHRNu, llvm::ARMISD::VRSHRN, llvm::ARMISD::VRSHRs, llvm::ARMISD::VRSHRu, llvm::ARMISD::VSHL, llvm::ARMISD::VSHLLi, llvm::ARMISD::VSHLLs, llvm::ARMISD::VSHLLu, llvm::ARMISD::VSHRN, llvm::ARMISD::VSHRs, llvm::ARMISD::VSHRu, llvm::ARMISD::VSLI, and llvm::ARMISD::VSRI.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformMULCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 8540 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isPowerOf2_32(), llvm::ARMSubtarget::isThumb1Only(), llvm::Log2_32(), PerformVMULCombine(), llvm::ISD::SHL, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformORCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

PerformORCombine - Target-specific dag combine xforms for ISD::OR.

Definition at line 8668 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ARMISD::BFI, llvm::ISD::BITCAST, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::countTrailingZeros(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), llvm::ARMSubtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::ARMSubtarget::hasT2ExtractPack(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::EVT::is128BitVector(), llvm::ARM::isBitFieldInvertedMask(), llvm::BuildVectorSDNode::isConstantSplat(), isNEONModifiedImm(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::SelectionDAG::MaskedValueIsZero(), llvm::OtherModImm, llvm::ISD::SHL, llvm::ISD::SRL, llvm::MVT::v2i32, llvm::MVT::v4i32, llvm::ARMISD::VBSL, and llvm::ARMISD::VORRIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformSELECT_CCCombine ( SDNode *  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST 
)
static

PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC to match f32 max/min patterns to use NEON vmax/vmin instructions.

Definition at line 10000 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::ARMISD::FMAX, llvm::ARMISD::FMIN, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTarget(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasNEON(), llvm::SelectionDAG::isEqualTo(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::SelectionDAG::isKnownNeverZero(), llvm::TargetMachine::Options, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, true, llvm::TargetOptions::UnsafeFPMath, and llvm::ARMSubtarget::useNEONForSinglePrecisionFP().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformShiftCombine ( SDNode *  N,
SelectionDAG &  DAG,
const ARMSubtarget *  ST 
)
static

PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them. As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.

Definition at line 9913 of file ARMISelLowering.cpp.

References llvm::ISD::BSWAP, llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasV6Ops(), llvm::TargetLoweringBase::isTypeLegal(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ARMISD::VSHL, llvm::ARMISD::VSHRs, and llvm::ARMISD::VSHRu.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformSTORECombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.

Definition at line 8969 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorTemplateCommon< T >::data(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::MVT::FIRST_INTEGER_VALUETYPE, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MemSDNode::getTBAAInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::SDNode::hasOneUse(), I, llvm::MVT::i64, llvm::MVT::i8, llvm::MemSDNode::isNonTemporal(), llvm::ISD::isNormalStore(), llvm::isPowerOf2_32(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::MVT::LAST_INTEGER_VALUETYPE, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::TokenFactor, and llvm::ARMISD::VMOVDRR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformSUBCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.

Definition at line 8480 of file ARMISelLowering.cpp.

References combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), and llvm::SDNode::hasOneUse().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVCVTCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3

Definition at line 9605 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vcvtfp2fxs, llvm::Intrinsic::arm_neon_vcvtfp2fxu, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ARMSubtarget::hasNEON(), llvm::ISD::INTRINSIC_WO_CHAIN, isConstVecPow2(), llvm::EVT::isVector(), llvm::Log2_64(), llvm::ISD::TRUNCATE, llvm::MVT::v2i32, and llvm::MVT::v4i32.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVDIVCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3

Definition at line 9656 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_neon_vcvtfxs2fp, llvm::Intrinsic::arm_neon_vcvtfxu2fp, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ARMSubtarget::hasNEON(), llvm::ISD::INTRINSIC_WO_CHAIN, isConstVecPow2(), llvm::EVT::isVector(), llvm::Log2_64(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVDUPLANECombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.

Definition at line 9540 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ARM_AM::decodeNEONModImm(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVECTOR_SHUFFLECombine ( SDNode *  N,
SelectionDAG &  DAG 
)
static

PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.

Definition at line 9274 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorTemplateCommon< T >::data(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ISD::UNDEF.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVMOVDRRCombine ( SDNode *  N,
SelectionDAG &  DAG 
)
static

PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.

Definition at line 8951 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SDNode::getValueType(), and llvm::ARMISD::VMOVRRD.

Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVMOVRRDCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI 
)
static

PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.

Definition at line 8908 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MVT::f64, llvm::ISD::FrameIndex, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::MemSDNode::isInvariant(), llvm::MemSDNode::isNonTemporal(), llvm::ISD::isNormalLoad(), llvm::MemSDNode::isVolatile(), llvm::A64DB::LD, llvm::TargetLowering::DAGCombinerInfo::RemoveFromWorklist(), and llvm::ARMISD::VMOVDRR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVMULCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding. vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2

Definition at line 8509 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasVMLxForwarding(), llvm::ISD::MUL, llvm::ISD::SUB, and std::swap().

Referenced by PerformMULCombine().

static SDValue PerformXORCombine ( SDNode *  N,
TargetLowering::DAGCombinerInfo &  DCI,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 8865 of file ARMISelLowering.cpp.

References combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::isThumb1Only(), and llvm::TargetLoweringBase::isTypeLegal().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static void ReplaceATOMIC_OP_64 ( SDNode *  Node,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG &  DAG 
)
static

Definition at line 6040 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i64, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

static void ReplaceREADCYCLECOUNTER ( SDNode *  N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG &  DAG,
const ARMSubtarget *  Subtarget 
)
static

Definition at line 6068 of file ARMISelLowering.cpp.

References llvm::Intrinsic::arm_mrc, llvm::array_lengthof(), llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasPerfMon(), llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::Other, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

static SDValue SkipExtensionForVMULL ( SDNode *  N,
SelectionDAG &  DAG 
)
static

SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value. The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.

Definition at line 5634 of file ARMISelLowering.cpp.

References AddRequiredExtensionForVMULL(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SmallVectorTemplateCommon< T >::data(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::TargetLoweringBase::isBigEndian(), llvm::A64DB::LD, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerMUL().

static SDValue SkipLoadExtensionForVMULL ( LoadSDNode *  LD,
SelectionDAG &  DAG 
)
static

SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension. If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.

Definition at line 5609 of file ARMISelLowering.cpp.

References llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), getExtensionTo64Bits(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemoryVT(), llvm::MemSDNode::getPointerInfo(), llvm::MemSDNode::isInvariant(), llvm::MemSDNode::isNonTemporal(), and llvm::MemSDNode::isVolatile().

Referenced by SkipExtensionForVMULL().

STATISTIC ( NumTailCalls  ,
"Number of tail calls"   
)
STATISTIC ( NumMovwMovt  ,
"Number of GAs materialized with movw + movt"   
)
STATISTIC ( NumLoopByVals  ,
"Number of loops generated for byval arguments"   
)

Variable Documentation

cl::opt<bool> ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
static
cl::opt<bool> EnableARMLongCalls("arm-long-calls", cl::Hidden, cl::desc("Generate calls via indirect call instructions"), cl::init(false))
cl::opt<bool> EnableARMTailCalls("arm-tail-calls", cl::Hidden, cl::desc("Generate tail calls (TEMPORARY OPTION)."), cl::init(false))
static
const uint16_t GPRArgRegs[]
static
Initial value:
= {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
}
R2
#define R2(n)

Definition at line 90 of file ARMISelLowering.cpp.

Referenced by llvm::f64AssignAAPCS().

Generated on Tue Mar 18 2014 10:39:45 for LLVM by Doxygen1.8.6
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