#include <ARMISelLowering.h>

Inheritance diagram for llvm::ARMTargetLowering:

Collaboration diagram for llvm::ARMTargetLowering:

Public Member Functions
	ARMTargetLowering (TargetMachine &TM)

virtual unsigned	getJumpTableEncoding () const

virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const

virtual void	ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const

virtual const char *	getTargetNodeName (unsigned Opcode) const
	This method returns the name of a target specific DAG node. More...

virtual bool	isSelectSupported (SelectSupportKind Kind) const

virtual EVT	getSetCCResultType (LLVMContext &Context, EVT VT) const
	getSetCCResultType - Return the value type to use for ISD::SETCC. More...

virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr MI, MachineBasicBlock MBB) const

virtual void	AdjustInstrPostInstrSelection (MachineInstr MI, SDNode Node) const

SDValue	PerformCMOVCombine (SDNode *N, SelectionDAG &DAG) const
	PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. More...

virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const

bool	isDesirableToTransformToIntegerOp (unsigned Opc, EVT VT) const

virtual bool	allowsUnalignedMemoryAccesses (EVT VT, bool *Fast) const

virtual EVT	getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const

virtual bool	isZExtFree (SDValue Val, EVT VT2) const

virtual bool	allowTruncateForTailCall (Type Ty1, Type Ty2) const

virtual bool	isLegalAddressingMode (const AddrMode &AM, Type *Ty) const

bool	isLegalT2ScaledAddressingMode (const AddrMode &AM, EVT VT) const

virtual bool	isLegalICmpImmediate (int64_t Imm) const

virtual bool	isLegalAddImmediate (int64_t Imm) const

virtual bool	getPreIndexedAddressParts (SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const

virtual bool	getPostIndexedAddressParts (SDNode N, SDNode Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const

virtual void	computeMaskedBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const

virtual bool	ExpandInlineAsm (CallInst *CI) const

ConstraintType	getConstraintType (const std::string &Constraint) const

ConstraintWeight	getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const

std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const

virtual void	LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const

const ARMSubtarget *	getSubtarget () const

virtual const TargetRegisterClass *	getRegClassFor (MVT VT) const

virtual unsigned	getMaximalGlobalOffset () const

virtual FastISel *	createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const

Sched::Preference	getSchedulingPreference (SDNode *N) const

bool	isShuffleMaskLegal (const SmallVectorImpl< int > &M, EVT VT) const

bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const

virtual bool	isFPImmLegal (const APFloat &Imm, EVT VT) const

virtual bool	getTgtMemIntrinsic (IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const

Public Member Functions inherited from llvm::TargetLowering
	TargetLowering (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual const MCExpr *	LowerCustomJumpTableEntry (const MachineJumpTableInfo , const MachineBasicBlock , unsigned, MCContext &) const

virtual SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
	Returns relocation base for the given PIC jumptable. More...

virtual const MCExpr *	getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const

bool	isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const

std::pair< SDValue, SDValue >	makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
	Returns a pair of (return value, chain). More...

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const

virtual unsigned	ComputeNumSignBitsForTargetNode (SDValue Op, unsigned Depth=0) const

SDValue	SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const

virtual bool	isGAPlusOffset (SDNode N, const GlobalValue &GA, int64_t &Offset) const

virtual bool	isTypeDesirableForOp (unsigned, EVT VT) const

virtual bool	IsDesirableToPromoteOp (SDValue, EVT &) const

std::pair< SDValue, SDValue >	LowerCallTo (CallLoweringInfo &CLI) const

virtual MVT	getTypeForExtArgOrReturn (MVT VT, ISD::NodeType) const

virtual const uint16_t *	getScratchRegisters (CallingConv::ID CC) const

virtual void	LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const

virtual AsmOperandInfoVector	ParseConstraints (ImmutableCallSite CS) const

virtual ConstraintWeight	getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const

virtual void	ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=0) const

virtual const char *	LowerXConstraint (EVT ConstraintVT) const

SDValue	BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
	Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...

SDValue	BuildSDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

SDValue	BuildUDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode > *Created) const
	Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...

Public Member Functions inherited from llvm::TargetLoweringBase
	TargetLoweringBase (const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)
	NOTE: The constructor takes ownership of TLOF. More...

virtual	~TargetLoweringBase ()

const TargetMachine &	getTargetMachine () const

const DataLayout *	getDataLayout () const

const TargetLoweringObjectFile &	getObjFileLowering () const

bool	isBigEndian () const

bool	isLittleEndian () const

virtual MVT	getPointerTy (uint32_t=0) const

unsigned	getPointerSizeInBits (uint32_t AS=0) const

unsigned	getPointerTypeSizeInBits (Type *Ty) const

virtual MVT	getScalarShiftAmountTy (EVT LHSTy) const

EVT	getShiftAmountTy (EVT LHSTy) const

virtual MVT	getVectorIdxTy () const

bool	isSelectExpensive () const
	Return true if the select operation is expensive for this target. More...

virtual bool	shouldSplitVectorElementType (EVT) const

bool	isIntDivCheap () const

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed. More...

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const

bool	isPow2DivCheap () const
	Return true if pow2 div is cheaper than a chain of srl/add/sra. More...

bool	isJumpExpensive () const

bool	isPredictableSelectExpensive () const

virtual bool	isLoadBitCastBeneficial (EVT, EVT) const

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const

BooleanContent	getBooleanContents (bool isVec) const

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference. More...

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const

virtual uint8_t	getRepRegClassCostFor (MVT VT) const

bool	isTypeLegal (EVT VT) const

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const

LegalizeTypeAction	getTypeAction (MVT VT) const

EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

virtual bool	canOpTrap (unsigned Op, EVT VT) const

virtual bool	isVectorClearMaskLegal (const SmallVectorImpl< int > &, EVT) const

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT) const

bool	isOperationLegalOrPromote (unsigned Op, EVT VT) const

bool	isOperationExpand (unsigned Op, EVT VT) const

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target. More...

LegalizeAction	getLoadExtAction (unsigned ExtType, MVT VT) const

bool	isLoadExtLegal (unsigned ExtType, EVT VT) const
	Return true if the specified load with extension is legal on this target. More...

LegalizeAction	getTruncStoreAction (MVT ValVT, MVT MemVT) const

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target. More...

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal on this target. More...

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const

EVT	getValueType (Type *Ty, bool AllowUnknown=false) const

MVT	getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType. More...

virtual unsigned	getByValTypeAlignment (Type *Ty) const

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require. More...

unsigned	getNumRegisters (LLVMContext &Context, EVT VT) const

virtual bool	ShouldShrinkFPConstant (EVT) const

bool	hasTargetDAGCombine (ISD::NodeType NT) const

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset. More...

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy. More...

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove. More...

virtual bool	isSafeMemOpType (MVT) const

bool	usesUnderscoreSetJmp () const
	Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...

bool	usesUnderscoreLongJmp () const
	Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...

bool	supportJumpTables () const
	Return whether the target can generate code for jump tables. More...

int	getMinimumJumpTableEntries () const

unsigned	getStackPointerRegisterToSaveRestore () const

unsigned	getExceptionPointerRegister () const

unsigned	getExceptionSelectorRegister () const

unsigned	getJumpBufSize () const

unsigned	getJumpBufAlignment () const

unsigned	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument. More...

unsigned	getMinFunctionAlignment () const
	Return the minimum function alignment. More...

unsigned	getPrefFunctionAlignment () const
	Return the preferred function alignment. More...

unsigned	getPrefLoopAlignment () const
	Return the preferred loop alignment. More...

bool	getInsertFencesForAtomic () const

virtual bool	getStackCookieLocation (unsigned &, unsigned &) const

virtual bool	isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast between SrcAS and DestAS is a noop. More...

virtual void	resetOperationActions ()
	Reset the operation actions based on target options. More...

virtual bool	GetAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const

virtual int	getScalingFactorCost (const AddrMode &AM, Type *Ty) const
	Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. More...

virtual bool	isTruncateFree (Type , Type ) const

virtual bool	isTruncateFree (EVT, EVT) const

virtual bool	isZExtFree (Type , Type ) const

virtual bool	isZExtFree (EVT, EVT) const

virtual bool	hasPairedLoad (Type *, unsigned &) const

virtual bool	hasPairedLoad (EVT, unsigned &) const

virtual bool	isFNegFree (EVT VT) const

virtual bool	isFAbsFree (EVT VT) const

virtual bool	isNarrowingProfitable (EVT, EVT) const

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall. More...

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall. More...

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall. More...

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall. More...

LegalizeKind	getTypeConversion (LLVMContext &Context, EVT VT) const

int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode. More...

std::pair< unsigned, MVT >	getTypeLegalizationCost (Type *Ty) const
	Estimate the cost of type-legalization and the legalized type. More...

Protected Member Functions
std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (MVT VT) const

Protected Member Functions inherited from llvm::TargetLoweringBase
void	initActions ()
	Initialize all of the actions to default values. More...

void	setBooleanContents (BooleanContent Ty)

void	setBooleanVectorContents (BooleanContent Ty)

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference. More...

void	setUseUnderscoreSetJmp (bool Val)

void	setUseUnderscoreLongJmp (bool Val)

void	setSupportJumpTables (bool Val)
	Indicate whether the target can generate code for jump tables. More...

void	setMinimumJumpTableEntries (int Val)

void	setStackPointerRegisterToSaveRestore (unsigned R)

void	setExceptionPointerRegister (unsigned R)

void	setExceptionSelectorRegister (unsigned R)

void	setSelectIsExpensive (bool isExpensive=true)

void	setJumpIsExpensive (bool isExpensive=true)

void	setIntDivIsCheap (bool isCheap=true)

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass. More...

void	setPow2DivIsCheap (bool isCheap=true)

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)

void	clearRegisterClasses ()
	Remove all register classes. More...

void	clearOperationActions ()
	Remove all operation actions. More...

void	computeRegisterProperties ()

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)

void	setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)

void	setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)

void	setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)

void	setTargetDAGCombine (ISD::NodeType NT)

void	setJumpBufSize (unsigned Size)
	Set the target's required jmp_buf buffer size (in bytes); default is 200. More...

void	setJumpBufAlignment (unsigned Align)

void	setMinFunctionAlignment (unsigned Align)
	Set the target's minimum function alignment (in log2(bytes)) More...

void	setPrefFunctionAlignment (unsigned Align)

void	setPrefLoopAlignment (unsigned Align)

void	setMinStackArgumentAlignment (unsigned Align)
	Set the minimum stack alignment of an argument (in log2(bytes)). More...

void	setInsertFencesForAtomic (bool fence)

bool	isLegalRC (const TargetRegisterClass *RC) const

Additional Inherited Members
Public Types inherited from llvm::TargetLowering
enum	ConstraintType { C_Register, C_RegisterClass, C_Memory, C_Other, C_Unknown }

enum	ConstraintWeight { CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2, CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better, CW_Constant = CW_Best, CW_Default = CW_Okay }

typedef std::vector< ArgListEntry >	ArgListTy

typedef std::vector < AsmOperandInfo >	AsmOperandInfoVector

Public Types inherited from llvm::TargetLoweringBase
enum	LegalizeAction { Legal, Promote, Expand, Custom }

enum	LegalizeTypeAction { TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat, TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector }

enum	BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

typedef std::pair < LegalizeTypeAction, EVT >	LegalizeKind

Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Attributes inherited from llvm::TargetLoweringBase
unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call. More...

unsigned	MaxStoresPerMemsetOptSize

unsigned	MaxStoresPerMemcpy
	Specify maximum bytes of store instructions per memcpy call. More...

unsigned	MaxStoresPerMemcpyOptSize

unsigned	MaxStoresPerMemmove
	Specify maximum bytes of store instructions per memmove call. More...

unsigned	MaxStoresPerMemmoveOptSize

bool	PredictableSelectIsExpensive

Detailed Description

Definition at line 239 of file ARMISelLowering.h.

Constructor & Destructor Documentation

ARMTargetLowering::ARMTargetLowering ( TargetMachine & TM )

explicit

Definition at line 170 of file ARMISelLowering.cpp.

Member Function Documentation

void ARMTargetLowering::AdjustInstrPostInstrSelection	(	MachineInstr *	MI,
		SDNode *	Node
	)		const

virtual

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented from llvm::TargetLowering.

Definition at line 7989 of file ARMISelLowering.cpp.

References llvm::MachineInstr::addOperand(), llvm::convertAddSubFlagsOpcode(), llvm::MachineOperand::CreateReg(), definesCPSR(), llvm::MachineInstr::getDesc(), llvm::TargetMachine::getInstrInfo(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDNode::hasAnyUseOfValue(), llvm::MachineInstr::hasOptionalDef(), llvm::MachineInstr::hasPostISelHook(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MCOperandInfo::isOptionalDef(), llvm::MachineOperand::isReg(), llvm::MCInstrDesc::OpInfo, llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDef(), and llvm::MachineOperand::setReg().

bool ARMTargetLowering::allowsUnalignedMemoryAccesses	(	EVT	VT,
		bool *	Fast
	)		const

virtual

allowsUnalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the specified type. Returns whether it is "fast" by reference in the second argument.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10214 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::allowsUnalignedMem(), llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasV7Ops(), llvm::MVT::i16, llvm::MVT::i8, llvm::TargetLoweringBase::isLittleEndian(), llvm::MVT::SimpleTy, and llvm::MVT::v2f64.

Referenced by getOptimalMemOpType().

bool ARMTargetLowering::allowTruncateForTailCall	(	Type *	,
		Type *
	)		const

virtual

Return true if a truncation from Ty1 to Ty2 is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10308 of file ARMISelLowering.cpp.

References llvm::EVT::getEVT(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), and llvm::TargetLoweringBase::isTypeLegal().

void ARMTargetLowering::computeMaskedBitsForTargetNode	(	const SDValue	Op,
		APInt &	KnownZero,
		APInt &	KnownOne,
		const SelectionDAG &	DAG,
		unsigned	Depth
	)		const

virtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 10717 of file ARMISelLowering.cpp.

References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::ARMISD::CMOV, llvm::SelectionDAG::ComputeMaskedBits(), llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::ARMISD::SUBC, and llvm::ARMISD::SUBE.

FastISel * ARMTargetLowering::createFastISel	(	FunctionLoweringInfo &	funcInfo,
		const TargetLibraryInfo *	libInfo
	)		const

virtual

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 1172 of file ARMISelLowering.cpp.

References llvm::ARM::createFastISel().

MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter	(	MachineInstr *	MI,
		MachineBasicBlock *	MBB
	)		const

virtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow.

Reimplemented from llvm::TargetLowering.

Definition at line 7611 of file ARMISelLowering.cpp.

bool ARMTargetLowering::ExpandInlineAsm ( CallInst * ) const

virtual

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented from llvm::TargetLowering.

Definition at line 10753 of file ARMISelLowering.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::dyn_cast(), llvm::InlineAsm::getAsmString(), llvm::IntegerType::getBitWidth(), llvm::CallInst::getCalledValue(), llvm::InlineAsm::getConstraintString(), llvm::Value::getType(), llvm::ARMSubtarget::hasV6Ops(), llvm::IntrinsicLowering::LowerToByteSwap(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::SplitString().

std::pair< const TargetRegisterClass *, uint8_t > ARMTargetLowering::findRepresentativeClass ( MVT VT ) const

protectedvirtual

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Reimplemented from llvm::TargetLoweringBase.

Definition at line 972 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::TargetLoweringBase::findRepresentativeClass(), llvm::MSP430ISD::RRC, llvm::MVT::SimpleTy, llvm::ARMSubtarget::useNEONForSinglePrecisionFP(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i64, and llvm::MVT::v8i8.

ARMTargetLowering::ConstraintType ARMTargetLowering::getConstraintType ( const std::string & Constraint ) const

virtual

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 10787 of file ARMISelLowering.cpp.

References llvm::TargetLowering::C_Memory, llvm::TargetLowering::C_Other, llvm::TargetLowering::C_RegisterClass, and llvm::TargetLowering::getConstraintType().

unsigned ARMTargetLowering::getJumpTableEncoding ( ) const

virtual

Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented from llvm::TargetLowering.

Definition at line 2343 of file ARMISelLowering.cpp.

References llvm::MachineJumpTableInfo::EK_Inline.

unsigned ARMTargetLowering::getMaximalGlobalOffset ( ) const

virtual

getMaximalGlobalOffset - Returns the maximal possible offset which can be used for loads / stores from the global.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1179 of file ARMISelLowering.cpp.

References llvm::ARMSubtarget::isThumb1Only().

EVT ARMTargetLowering::getOptimalMemOpType	(	uint64_t	,
		unsigned	,
		unsigned	,
		bool	,
		bool	,
		bool	,
		MachineFunction &
	)		const

virtual

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10253 of file ARMISelLowering.cpp.

References allowsUnalignedMemoryAccesses(), llvm::MVT::f64, llvm::CallingConv::Fast, llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::AttributeSet::hasAttribute(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::i16, llvm::MVT::i32, memOpAlign(), llvm::Attribute::NoImplicitFloat, llvm::MVT::Other, and llvm::MVT::v2f64.

bool ARMTargetLowering::getPostIndexedAddressParts	(	SDNode *	N,
		SDNode *	Op,
		SDValue &	Base,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG
	)		const

virtual

getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented from llvm::TargetLowering.

Definition at line 10669 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, getARMIndexedAddressParts(), llvm::SDNode::getOpcode(), getT2IndexedAddressParts(), llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::A64DB::LD, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::ISD::SEXTLOAD, and std::swap().

bool ARMTargetLowering::getPreIndexedAddressParts	(	SDNode *	N,
		SDValue &	Base,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG
	)		const

virtual

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented from llvm::TargetLowering.

Definition at line 10631 of file ARMISelLowering.cpp.

References getARMIndexedAddressParts(), llvm::SDValue::getNode(), getT2IndexedAddressParts(), llvm::ISD::isSEXTLoad(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::A64DB::LD, llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, and llvm::ISD::SEXTLOAD.

const TargetRegisterClass * ARMTargetLowering::getRegClassFor ( MVT VT ) const

virtual

getRegClassFor - Return the register class that should be used for the specified value type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1157 of file ARMISelLowering.cpp.

References llvm::TargetLoweringBase::getRegClassFor(), llvm::ARMSubtarget::hasNEON(), llvm::MVT::v4i64, and llvm::MVT::v8i64.

RCPair ARMTargetLowering::getRegForInlineAsmConstraint	(	const std::string &	Constraint,
		MVT	VT
	)		const

virtual

Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer..

Reimplemented from llvm::TargetLowering.

Definition at line 10847 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MVT::getSizeInBits(), llvm::ARMSubtarget::isThumb(), and llvm::MVT::Other.

Sched::Preference ARMTargetLowering::getSchedulingPreference ( SDNode * ) const

virtual

Some scheduler, e.g. hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1183 of file ARMISelLowering.cpp.

References llvm::MCInstrInfo::get(), llvm::TargetMachine::getInstrInfo(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getNumValues(), llvm::InstrItineraryData::getOperandCycle(), llvm::MCInstrDesc::getSchedClass(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDNode::getValueType(), llvm::MVT::Glue, llvm::Sched::ILP, llvm::InstrItineraryData::isEmpty(), llvm::EVT::isFloatingPoint(), llvm::SDNode::isMachineOpcode(), llvm::EVT::isVector(), llvm::MVT::Other, llvm::Sched::RegPressure, and TII.

EVT ARMTargetLowering::getSetCCResultType	(	LLVMContext &	Context,
		EVT	VT
	)		const

virtual

getSetCCResultType - Return the value type to use for ISD::SETCC.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1150 of file ARMISelLowering.cpp.

References llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::getPointerTy(), and llvm::EVT::isVector().

TargetLowering::ConstraintWeight ARMTargetLowering::getSingleConstraintMatchWeight	(	AsmOperandInfo &	info,
		const char *	constraint
	)		const

virtual

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 10815 of file ARMISelLowering.cpp.

References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::Value::getType(), llvm::Type::isFloatingPointTy(), llvm::Type::isIntegerTy(), and llvm::ARMSubtarget::isThumb().

const ARMSubtarget* llvm::ARMTargetLowering::getSubtarget ( ) const

inline

Definition at line 354 of file ARMISelLowering.h.

const char * ARMTargetLowering::getTargetNodeName ( unsigned Opcode ) const

virtual

This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 1008 of file ARMISelLowering.cpp.

bool ARMTargetLowering::getTgtMemIntrinsic	(	IntrinsicInfo &	Info,
		const CallInst &	I,
		unsigned	Intrinsic
	)		const

virtual

getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes. The associated MachineMemOperands record the alignment specified in the intrinsic calls.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11144 of file ARMISelLowering.cpp.

bool ARMTargetLowering::isDesirableToTransformToIntegerOp	(	unsigned	,
		EVT
	)		const

virtual

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented from llvm::TargetLowering.

Definition at line 10209 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::ISD::LOAD, and llvm::ISD::STORE.

bool ARMTargetLowering::isFPImmLegal	(	const APFloat &	Imm,
		EVT	VT
	)		const

virtual

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 11131 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::ARM_AM::getFP32Imm(), llvm::ARM_AM::getFP64Imm(), and llvm::ARMSubtarget::hasVFP3().

bool ARMTargetLowering::isLegalAddImmediate ( int64_t Imm ) const

virtual

isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.

isLegalAddImmediate - Return true if the specified immediate is a legal add or sub immediate, that is the target has add or sub instructions which can add a register with the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10532 of file ARMISelLowering.cpp.

References llvm::abs64(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::ARMSubtarget::isThumb(), and llvm::ARMSubtarget::isThumb2().

bool ARMTargetLowering::isLegalAddressingMode	(	const AddrMode &	AM,
		Type *	Ty
	)		const

virtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10455 of file ARMISelLowering.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::getValueType(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i64, llvm::MVT::i8, isLegalAddressImmediate(), isLegalT2ScaledAddressingMode(), llvm::isPowerOf2_32(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::MVT::isVoid, llvm::TargetLoweringBase::AddrMode::Scale, and llvm::MVT::SimpleTy.

bool ARMTargetLowering::isLegalICmpImmediate ( int64_t Imm ) const

virtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10518 of file ARMISelLowering.cpp.

References llvm::abs64(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::ARMSubtarget::isThumb(), and llvm::ARMSubtarget::isThumb2().

bool ARMTargetLowering::isLegalT2ScaledAddressingMode	(	const AddrMode &	AM,
		EVT	VT
	)		const

Definition at line 10420 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i64, llvm::MVT::i8, llvm::isPowerOf2_32(), llvm::MVT::isVoid, llvm::TargetLoweringBase::AddrMode::Scale, and llvm::MVT::SimpleTy.

Referenced by isLegalAddressingMode().

bool ARMTargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const

virtual

Return true if folding a constant offset with the given GlobalAddress is legal. It is frequently not legal in PIC relocation models.

Reimplemented from llvm::TargetLowering.

Definition at line 11110 of file ARMISelLowering.cpp.

virtual bool llvm::ARMTargetLowering::isSelectSupported ( SelectSupportKind Kind ) const

inlinevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 255 of file ARMISelLowering.h.

References llvm::TargetLoweringBase::ScalarCondVectorVal.

bool ARMTargetLowering::isShuffleMaskLegal	(	const SmallVectorImpl< int > &	M,
		EVT	VT
	)		const

virtual

isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 5139 of file ARMISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isReverseMask(), llvm::ShuffleVectorSDNode::isSplatMask(), isVEXTMask(), isVREVMask(), isVTBLMask(), isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), PerfectShuffleTable, llvm::MVT::v16i8, and llvm::MVT::v8i16.

bool ARMTargetLowering::isZExtFree	(	SDValue	Val,
		EVT	VT2
	)		const

virtual

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Reimplemented from llvm::TargetLoweringBase.

Definition at line 10287 of file ARMISelLowering.cpp.

References llvm::SDValue::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::ISD::LOAD, and llvm::MVT::SimpleTy.

void ARMTargetLowering::LowerAsmOperandForConstraint	(	SDValue	Op,
		std::string &	Constraint,
		std::vector< SDValue > &	Ops,
		SelectionDAG &	DAG
	)		const

virtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 10896 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::ConstantSDNode::getSExtValue(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::ARM_AM::isThumbImmShiftedVal(), and llvm::TargetLowering::LowerAsmOperandForConstraint().

SDValue ARMTargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

virtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Reimplemented from llvm::TargetLowering.

Definition at line 6106 of file ARMISelLowering.cpp.

References llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantFP, llvm::ISD::ConstantPool, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, ExpandBITCAST(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FCOPYSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAMEADDR, llvm::ISD::FSINCOS, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::ISD::GLOBAL_OFFSET_TABLE, llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ARMSubtarget::isTargetDarwin(), llvm_unreachable, LowerADDC_ADDE_SUBC_SUBE(), LowerATOMIC_FENCE(), LowerAtomicLoadStore(), LowerCONCAT_VECTORS(), LowerConstantPool(), LowerCTPOP(), LowerCTTZ(), LowerEXTRACT_VECTOR_ELT(), LowerFP_TO_INT(), LowerINSERT_VECTOR_ELT(), LowerINT_TO_FP(), LowerMUL(), LowerPREFETCH(), LowerSDIV(), LowerShift(), LowerUDIV(), LowerVASTART(), LowerVECTOR_SHUFFLE(), LowerVSETCC(), llvm::ISD::MUL, llvm::ISD::PREFETCH, llvm::ISD::RETURNADDR, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::VASTART, and llvm::ISD::VECTOR_SHUFFLE.

SDValue ARMTargetLowering::PerformCMOVCombine	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.

FIXME: Turn this into a target neutral optimization?

Definition at line 10085 of file ARMISelLowering.cpp.

References llvm::ISD::AssertZext, llvm::ARMISD::CMOV, llvm::ARMISD::CMPZ, llvm::SelectionDAG::ComputeMaskedBits(), llvm::ARMCC::EQ, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, llvm::ARMCC::NE, and llvm::ISD::SETNE.

Referenced by PerformDAGCombine().

SDValue ARMTargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

virtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented from llvm::TargetLowering.

Definition at line 10147 of file ARMISelLowering.cpp.

void ARMTargetLowering::ReplaceNodeResults	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)		const

virtual

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 6168 of file ARMISelLowering.cpp.

The documentation for this class was generated from the following files:

Public Member Functions

Protected Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation