LLVM API Documentation
#include "X86ISelLowering.h"#include "Utils/X86ShuffleDecode.h"#include "X86.h"#include "X86CallingConv.h"#include "X86InstrBuilder.h"#include "X86TargetMachine.h"#include "X86TargetObjectFile.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/StringExtras.h"#include "llvm/ADT/VariadicFunction.h"#include "llvm/CodeGen/IntrinsicLowering.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineModuleInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/IR/CallingConv.h"#include "llvm/IR/Constants.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/GlobalAlias.h"#include "llvm/IR/GlobalVariable.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/LLVMContext.h"#include "llvm/MC/MCAsmInfo.h"#include "llvm/MC/MCContext.h"#include "llvm/MC/MCExpr.h"#include "llvm/MC/MCSymbol.h"#include "llvm/Support/CallSite.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Target/TargetOptions.h"#include <bitset>#include <cctype>#include "X86GenCallingConv.inc"
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| #define | DEBUG_TYPE "x86-isel" |
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| enum | StructReturnType { NotStructReturn, RegStructReturn, StackStructReturn } |
| #define DEBUG_TYPE "x86-isel" |
Definition at line 15 of file X86ISelLowering.cpp.
| enum StructReturnType |
CallIsStructReturn - Determines whether a call uses struct return semantics.
| Enumerator | |
|---|---|
| NotStructReturn | |
| RegStructReturn | |
| StackStructReturn | |
Definition at line 2037 of file X86ISelLowering.cpp.
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ArgsAreStructReturn - Determines whether a function uses struct return semantics.
Definition at line 2058 of file X86ISelLowering.cpp.
References llvm::SmallVectorBase::empty(), llvm::ISD::ArgFlagsTy::isInReg(), llvm::ISD::ArgFlagsTy::isSRet(), NotStructReturn, RegStructReturn, and StackStructReturn.
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Definition at line 5622 of file X86ISelLowering.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::A64CC::NV, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::ISD::UNDEF.
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Definition at line 2043 of file X86ISelLowering.cpp.
References llvm::SmallVectorBase::empty(), llvm::ISD::ArgFlagsTy::isInReg(), llvm::ISD::ArgFlagsTy::isSRet(), NotStructReturn, RegStructReturn, and StackStructReturn.
CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector so it can be folded inside ANDNP.
Definition at line 17574 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ISD::INSERT_SUBVECTOR, llvm::EVT::is256BitVector(), llvm::ISD::isBuildVectorAllOnes(), and llvm::ISD::UNDEF.
Referenced by PerformAndCombine().
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Definition at line 15235 of file X86ISelLowering.cpp.
References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::isLiveIn(), llvm::next(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().
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Definition at line 17048 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::dyn_cast(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::X86::GetOppositeBranchCondition(), llvm::SDValue::getResNo(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasAnyUseOfValue(), llvm::X86ISD::RDRAND, llvm::X86ISD::RDSEED, llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::X86ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by PerformBrCondCombine(), PerformCMOVCombine(), and PerformSETCCCombine().
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Definition at line 19283 of file X86ISelLowering.cpp.
References llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorTemplateCommon< T >::end(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by llvm::X86TargetLowering::ExpandInlineAsm().
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Definition at line 17498 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::X86ISD::CMP, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::X86::COND_NP, llvm::X86::COND_P, llvm::ISD::CopyToReg, llvm::MVT::f32, llvm::MVT::f64, llvm::X86ISD::FSETCCsd, llvm::X86ISD::FSETCCss, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::MVT::i8, isAndOrOfSetCCs(), llvm::ISD::SELECT, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), and llvm::ISD::ZERO_EXTEND.
Referenced by PerformAndCombine(), and PerformOrCombine().
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CommuteVectorShuffle - Swap vector_shuffle operands as well as values in their permute mask.
Definition at line 4566 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming the two vector operands have swapped position.
Definition at line 3703 of file X86ISelLowering.cpp.
Referenced by isHorizontalBinOp(), LowerVECTOR_SHUFFLE_128v4(), and LowerVECTOR_SHUFFLEv32i8().
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Definition at line 3861 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getVectorShuffle(), isUndefOrEqual(), llvm::ISD::UNDEF, llvm::MVT::v8f32, and llvm::MVT::v8i32.
Referenced by LowerVECTOR_SHUFFLE_256().
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Concat two 128-bit vectors into a 256 bit vector using VINSERTF128 instructions. This is used because creating CONCAT_VECTOR nodes of BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower large BUILD_VECTORS.
Definition at line 165 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getUNDEF(), and Insert128BitVector().
Referenced by getOnesVector(), and LowerAVXCONCAT_VECTORS().
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Definition at line 172 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getUNDEF(), and Insert256BitVector().
Referenced by LowerAVXCONCAT_VECTORS().
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CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment information specified by the specific parameter attribute. The copy will be passed as a byval function parameter.
Definition at line 2075 of file X86ISelLowering.cpp.
References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), and llvm::MVT::i32.
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Definition at line 179 of file X86ISelLowering.cpp.
References llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isTargetCOFF(), llvm::X86Subtarget::isTargetELF(), llvm::X86Subtarget::isTargetEnvMacho(), llvm::X86Subtarget::isTargetLinux(), and llvm_unreachable.
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EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a vector of type 'VT', see if the elements can be replaced by a single large load which has the same value as a build_vector whose operands are 'elts'.
Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
FIXME: we'd also like to handle the case where the last elements are zero rather than undef via VZEXT_LOAD, but we do not detect that case today. There's even a handy isZeroNode for that purpose.
Definition at line 5397 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::ISD::BITCAST, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasAnyUseOfValue(), llvm::MVT::i64, llvm::SelectionDAG::InferPtrAlignment(), llvm::SelectionDAG::isConsecutiveLoad(), llvm::MemSDNode::isInvariant(), llvm::ISD::isNON_EXTLoad(), llvm::MemSDNode::isNonTemporal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::MemSDNode::isVolatile(), llvm::A64DB::LD, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::TokenFactor, llvm::ISD::UNDEF, llvm::SelectionDAG::UpdateNodeOperands(), llvm::MVT::v2i64, and llvm::X86ISD::VZEXT_LOAD.
Referenced by PerformShuffleCombine().
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Definition at line 14876 of file X86ISelLowering.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::X86::AddrNumOperands, llvm::BuildMI(), llvm::TargetOpcode::COPY, llvm::N86::EAX, llvm::N86::ECX, llvm::N86::EDX, llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::X86Subtarget::is64Bit().
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter().
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Definition at line 14841 of file X86ISelLowering.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::TargetOpcode::COPY, llvm::N86::ECX, llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), and llvm::MachineInstr::setMemRefs().
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter().
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Definition at line 14804 of file X86ISelLowering.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::TargetOpcode::COPY, llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), and llvm::MachineInstr::setMemRefs().
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter().
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EmitTailCallStoreRetAddr - Emit a store of the return address if tail call optimization is performed and it is required (FPDiff!=0).
Definition at line 2479 of file X86ISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), and llvm::SelectionDAG::getStore().
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Utility function to emit xbegin specifying the start of an RTM region.
Definition at line 14067 of file X86ISelLowering.cpp.
References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::TargetOpcode::COPY, llvm::MachineFunction::CreateMachineBasicBlock(), llvm::N86::EAX, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MCInstrInfo::get(), llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), I, llvm::MachineFunction::insert(), llvm::next(), llvm::MachineBasicBlock::splice(), and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter().
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Generate a DAG to grab 128-bits from a vector > 128 bits. This sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128 or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4 instructions or a simple subregister reference. Idx is an index in the 128 bits we want. It need not be aligned to a 128-bit bounday. That makes lowering EXTRACT_VECTOR_ELT operations easier.
Definition at line 103 of file X86ISelLowering.cpp.
References ExtractSubVector(), llvm::SDValue::getValueType(), llvm::EVT::is256BitVector(), and llvm::EVT::is512BitVector().
Referenced by Lower256IntArith(), Lower256IntVSETCC(), LowerEXTRACT_SUBVECTOR(), LowerShift(), LowerVECTOR_SHUFFLE_256(), LowerVectorBroadcast(), PerformSELECTCombine(), PerformShuffleCombine256(), PerformSTORECombine(), and PromoteSplat().
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Generate a DAG to grab 256-bits from a 512-bit vector.
Definition at line 111 of file X86ISelLowering.cpp.
References ExtractSubVector(), llvm::SDValue::getValueType(), and llvm::EVT::is512BitVector().
Referenced by LowerEXTRACT_SUBVECTOR().
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Extract one bit from mask vector, like v16i1 or v8i1. AVX-512 feature.
Definition at line 16359 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::MipsISD::Ext, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::i1, llvm::MVT::i8, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::MVT::v16i1, llvm::MVT::v16i32, llvm::MVT::v8i1, llvm::MVT::v8i64, and llvm::ISD::ZERO_EXTEND.
Referenced by PerformEXTRACT_VECTOR_ELTCombine().
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Definition at line 62 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDNode::op_begin(), and llvm::ISD::UNDEF.
Referenced by Extract128BitVector(), and Extract256BitVector().
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FuncIsMadeTailCallSafe - Return true if the function is being made into a tailcall target by changing its ABI.
Definition at line 2112 of file X86ISelLowering.cpp.
References IsTailCallConvention().
Definition at line 14123 of file X86ISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, and llvm::MVT::SimpleTy.
Definition at line 4496 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm_unreachable.
Referenced by llvm::X86::getExtractVEXTRACT128Immediate(), and llvm::X86::getExtractVEXTRACT256Immediate().
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Definition at line 11723 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::dyn_cast(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getZeroVector(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i8, and llvm::MVT::Other.
Referenced by LowerINTRINSIC_W_CHAIN().
Definition at line 4511 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), and llvm_unreachable.
Referenced by llvm::X86::getInsertVINSERT128Immediate(), and llvm::X86::getInsertVINSERT256Immediate().
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getLegalSplat - Generate a legal splat with supported x86 shuffles
Definition at line 4849 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm_unreachable, llvm::MVT::v4f32, and llvm::MVT::v8f32.
Referenced by PromoteSplat().
Definition at line 14136 of file X86ISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, and llvm::MVT::SimpleTy.
getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.
Definition at line 1565 of file X86ISelLowering.cpp.
Referenced by llvm::X86TargetLowering::getByValTypeAlignment().
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Definition at line 11744 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), getZeroVector(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i8, llvm::MVT::Other, and llvm::ISD::UNDEF.
Referenced by LowerINTRINSIC_W_CHAIN().
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Definition at line 7005 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), llvm::X86ISD::MOVDDUP, and llvm::MVT::v2f64.
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Definition at line 7035 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), llvm::X86ISD::MOVHLPS, llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v4f32, and llvm::MVT::v4i32.
getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd operation of specified width.
Definition at line 4793 of file X86ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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Definition at line 7016 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v2f64, llvm::MVT::v2i64, and llvm::MVT::v4f32.
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Definition at line 7051 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getOperand(), getShuffleSHUFImmediate(), llvm::SDValue::getSimpleValueType(), getTargetShuffleNode(), llvm::MVT::getVectorNumElements(), isMOVLMask(), MayFoldIntoStore(), MayFoldVectorLoad(), llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::X86ISD::SHUFP, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::MVT::v4i32.
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Definition at line 11784 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i8, and llvm::MVT::Other.
Referenced by LowerINTRINSIC_W_CHAIN().
Definition at line 14198 of file X86ISelLowering.cpp.
References llvm_unreachable.
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Definition at line 14216 of file X86ISelLowering.cpp.
References llvm_unreachable.
Definition at line 14149 of file X86ISelLowering.cpp.
References llvm_unreachable.
Definition at line 14169 of file X86ISelLowering.cpp.
References llvm_unreachable.
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getNumOfConsecutiveZeros - Return the number of elements of a vector shuffle operation which come from a consecutively from a zero. The search can start in two different directions, from left or right. We count undefs as zeros until PreferredNum is reached.
Definition at line 5081 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), getShuffleScalarElt(), llvm::X86::isZeroNode(), and llvm::ISD::UNDEF.
Referenced by isVectorShiftLeft(), and isVectorShiftRight().
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getOnesVector - Returns a vector of specified type with all bits set. Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their original type, ensuring they get CSE'd.
Definition at line 4758 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, Concat128BitVectors(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::isVector(), llvm_unreachable, llvm::MVT::v4i32, and llvm::MVT::v8i32.
Definition at line 14229 of file X86ISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::MVT::i32, llvm::MVT::i8, llvm_unreachable, and llvm::MVT::SimpleTy.
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Definition at line 11766 of file X86ISelLowering.cpp.
References llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i8, and llvm::MVT::Other.
Referenced by LowerINTRINSIC_W_CHAIN().
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getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
Definition at line 4473 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), and llvm::MVT::is512BitVector().
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getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
Definition at line 4425 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::MVT::v16i16, and llvm::MVT::v8i16.
Referenced by LowerVECTOR_SHUFFLEv8i16().
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getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
Definition at line 4449 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::MVT::v16i16, and llvm::MVT::v8i16.
Referenced by LowerVECTOR_SHUFFLEv8i16().
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getShuffleScalarElt - Returns the scalar element that will make up the ith element of the result of the vector shuffle.
Definition at line 5015 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), getTargetShuffleMask(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorNumElements(), isTargetShuffle(), llvm::EVT::isVector(), and llvm::ISD::SCALAR_TO_VECTOR.
Referenced by getNumOfConsecutiveZeros(), and PerformShuffleCombine().
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getShuffleSHUFImmediate - Return the appropriate immediate to shuffle the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. Handles 128-bit and 256-bit.
Definition at line 4395 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), and llvm::MVT::getVectorNumElements().
Referenced by getMOVLP().
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getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified vector of zero or undef vector. This produces a shuffle where the low element of V2 is swizzled into the zero/undef vector, landing at element Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
Definition at line 4917 of file X86ISelLowering.cpp.
References llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), getZeroVector(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::X86TargetLowering::BuildFILD().
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getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
Definition at line 4134 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getSimpleValueType(), and llvm::MVT::getVectorNumElements().
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getTargetShuffleMask - Calculates the shuffle mask corresponding to the target specific opcode. Returns true if the Mask could be calculated. Sets IsUnary to true if only uses one source.
Definition at line 4935 of file X86ISelLowering.cpp.
References llvm::DecodeMOVHLPSMask(), llvm::DecodeMOVLHPSMask(), llvm::DecodePALIGNRMask(), llvm::DecodePSHUFHWMask(), llvm::DecodePSHUFLWMask(), llvm::DecodePSHUFMask(), llvm::DecodeSHUFPMask(), llvm::DecodeUNPCKHMask(), llvm::DecodeUNPCKLMask(), llvm::DecodeVPERM2X128Mask(), llvm::DecodeVPERMMask(), llvm::SmallVectorBase::empty(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MVT::getVectorNumElements(), llvm_unreachable, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::PALIGNR, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::X86ISD::SHUFP, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, and llvm::X86ISD::VPERMILP.
Referenced by getShuffleScalarElt(), and XFormVExtractWithShuffleIntoLoad().
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Definition at line 3289 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm_unreachable, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVSHDUP, and llvm::X86ISD::MOVSLDUP.
Referenced by llvm::X86TargetLowering::BuildFILD(), getMOVDDup(), getMOVHighToLow(), getMOVLowToHigh(), getMOVLP(), and LowerVECTOR_SHUFFLEv8i16().
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Definition at line 3300 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i8, llvm_unreachable, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::VPERMI, and llvm::X86ISD::VPERMILP.
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Definition at line 3314 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i8, llvm_unreachable, llvm::X86ISD::PALIGNR, llvm::X86ISD::SHUFP, and llvm::X86ISD::VPERM2X128.
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Definition at line 3327 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm_unreachable, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::X86ISD::UNPCKH, and llvm::X86ISD::UNPCKL.
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Definition at line 10967 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::MVT::i8, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRAI, and llvm::X86ISD::VSRLI.
Referenced by getTargetVShiftNode(), LowerMUL(), LowerScalarImmediateShift(), and LowerShift().
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Definition at line 10987 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), getTargetVShiftByConstNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm_unreachable, llvm::MVT::v4i32, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, and llvm::X86ISD::VSRLI.
Referenced by LowerINTRINSIC_WO_CHAIN(), and LowerScalarVariableShift().
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Definition at line 8132 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFrameInfo(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::TLSModel::LocalDynamic, llvm::MVT::Other, llvm::MachineFrameInfo::setAdjustsStack(), llvm::X86ISD::TLSADDR, and llvm::X86ISD::TLSBASEADDR.
Referenced by LowerToTLSGeneralDynamicModel32(), LowerToTLSGeneralDynamicModel64(), and LowerToTLSLocalDynamicModel().
getUnpackh - Returns a vector_shuffle node for an unpackh operation.
Definition at line 4816 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by LowerAVXExtend(), and PromoteSplati8i16().
getUnpackl - Returns a vector_shuffle node for an unpackl operation.
Definition at line 4804 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::X86TargetLowering::BuildFILD(), LowerAVXExtend(), and PromoteSplati8i16().
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getVShift - Return a vector logical shift node.
Definition at line 5301 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::MVT::v2i64, llvm::X86ISD::VSHLDQ, and llvm::X86ISD::VSRLDQ.
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getVZextMovL - Return a zero-extending vector move low node.
Definition at line 6701 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), isScalarLoadToVector(), llvm::A64DB::LD, llvm::ISD::SCALAR_TO_VECTOR, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::X86ISD::VZEXT_MOVL.
Referenced by NormalizeVectorShuffle().
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getZeroVector - Returns a vector of specified type with all zero elements.
Definition at line 4714 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::MVT::f32, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetConstantFP(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::EVT::is512BitVector(), llvm::EVT::isVector(), llvm_unreachable, llvm::MVT::v16i32, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8f32, and llvm::MVT::v8i32.
Referenced by getGatherNode(), getMGatherNode(), getShuffleVectorZeroOrUndef(), LowerAVXExtend(), LowerBuildVectorv16i8(), LowerBuildVectorv8i16(), LowerScalarImmediateShift(), NormalizeVectorShuffle(), performShiftToAllZeros(), and PerformShuffleCombine256().
hasFPCMov - is there a floating point cmov for the specific X86 condition code. Current x86 isa includes the following FP cmov instructions: fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
Definition at line 3509 of file X86ISelLowering.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::X86::COND_NP, and llvm::X86::COND_P.
Referenced by PerformCMOVCombine().
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Generate a DAG to put 128-bits into a vector > 128 bits. This sets things up to match to an AVX VINSERTF128/VINSERTI128 or AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a simple superregister reference. Idx is an index in the 128 bits we want. It need not be aligned to a 128-bit bounday. That makes lowering INSERT_VECTOR_ELT operations easier.
Definition at line 147 of file X86ISelLowering.cpp.
References llvm::SDValue::getValueType(), InsertSubVector(), and llvm::EVT::is128BitVector().
Referenced by Concat128BitVectors(), LowerINSERT_SUBVECTOR(), LowerSCALAR_TO_VECTOR(), PerformLOADCombine(), and PerformShuffleCombine256().
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Definition at line 154 of file X86ISelLowering.cpp.
References llvm::SDValue::getValueType(), InsertSubVector(), and llvm::EVT::is256BitVector().
Referenced by Concat256BitVectors(), and LowerINSERT_SUBVECTOR().
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Definition at line 117 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::ISD::INSERT_SUBVECTOR, and llvm::ISD::UNDEF.
Referenced by Insert128BitVector(), and Insert256BitVector().
Definition at line 9681 of file X86ISelLowering.cpp.
References llvm::dyn_cast(), and llvm::ConstantSDNode::isAllOnesValue().
Referenced by PerformAndCombine(), and PerformXorCombine().
Definition at line 10459 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::OR, and llvm::X86ISD::SETCC.
Referenced by CMPEQCombine().
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Return true if the calling convention is a C calling convention.
Definition at line 2093 of file X86ISelLowering.cpp.
References llvm::CallingConv::C, llvm::CallingConv::X86_64_SysV, and llvm::CallingConv::X86_64_Win64.
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isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse of what x86 movss want. X86 movs requires the lowest element to be lowest element of vector 2 and the other elements to come from vector 1 in order.
Definition at line 4233 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), isUndefOrEqual(), and isUndefOrInRange().
Referenced by llvm::X86TargetLowering::isVectorClearMaskLegal(), and NormalizeVectorShuffle().
isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" and return the operands for the horizontal operation in LHS and RHS. A horizontal operation performs the binary operation on successive elements of its first operand, then on successive elements of its second operand, returning the resulting values in a vector. For example, if A = < float a0, float a1, float a2, float a3 > and B = < float b0, float b1, float b2, float b3 > then the result of doing a horizontal operation on A and B is A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. In short, LHS and RHS are inspected to see if LHS op RHS is of the form A horizontal-op B, for some already available A and B, and if so then LHS is set to A, RHS to B, and the routine returns 'true'. Note that the binary operation should have the property that if one of the operands is UNDEF then the result is UNDEF.
Definition at line 18469 of file X86ISelLowering.cpp.
References llvm::ARM_PROC::A, llvm::ArrayRef< T >::begin(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::CallingConv::C, CommuteVectorShuffleMask(), llvm::ArrayRef< T >::end(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::ISD::UNDEF, and llvm::ISD::VECTOR_SHUFFLE.
Referenced by PerformAddCombine(), PerformFADDCombine(), PerformFSUBCombine(), and PerformSubCombine().
isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to 128-bit version of MOVDDUP.
Definition at line 4325 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().
isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to 256-bit version of MOVDDUP.
Definition at line 4305 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), and isUndefOrEqual().
isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, <2, 3, 2, 3>
Definition at line 3798 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().
isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVHLPS.
Definition at line 3779 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().
isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVLHPS.
Definition at line 3837 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().
isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSS, MOVSD, and MOVD, i.e. setting the lowest element.
Definition at line 4079 of file X86ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), and isUndefOrEqual().
Referenced by getMOVLP(), llvm::X86TargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isVectorClearMaskLegal(), and NormalizeVectorShuffle().
isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
Definition at line 3815 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().
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isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSHDUP. Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
Definition at line 4257 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasSSE3(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().
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isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to MOVSLDUP. Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
Definition at line 4281 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasSSE3(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().
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isPALIGNRMask - Return true if the node specifies a shuffle of elements that is suitable for input to PALIGNR.
Definition at line 3630 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSSE3(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), isUndefOrEqual(), and isUndefOrInRange().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
Definition at line 4157 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and isUndefOrInRange().
isPSHUFDMask - Return true if the node specifies a shuffle of elements that is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference the second operand.
Definition at line 3562 of file X86ISelLowering.cpp.
References llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, and llvm::MVT::v4i32.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
isPSHUFHWMask - Return true if the node specifies a shuffle of elements that is suitable for input to PSHUFHW.
Definition at line 3572 of file X86ISelLowering.cpp.
References isSequentialOrUndefInRange(), isUndefOrInRange(), llvm::MVT::v16i16, and llvm::MVT::v8i16.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
isPSHUFLWMask - Return true if the node specifies a shuffle of elements that is suitable for input to PSHUFLW.
Definition at line 3601 of file X86ISelLowering.cpp.
References isSequentialOrUndefInRange(), isUndefOrInRange(), llvm::MVT::v16i16, and llvm::MVT::v8i16.
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
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isScalarLoadToVector - Returns true if the node is a scalar load that is promoted to a vector. It also returns the LoadSDNode by reference if required.
Definition at line 4607 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isNON_EXTLoad(), llvm::A64DB::LD, N, and llvm::ISD::SCALAR_TO_VECTOR.
Referenced by getVZextMovL(), and ShouldXformToMOVLP().
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isSequentialOrUndefInRange - Return true if every element in Mask, beginning from position Pos and ending in Pos+Size, falls within the specified sequential range (L, L+Pos]. or is undef.
Definition at line 3551 of file X86ISelLowering.cpp.
References isUndefOrEqual().
Referenced by isPSHUFHWMask(), isPSHUFLWMask(), and isVPERM2X128Mask().
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isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the same as extracting the high 128-bit part of 256-bit vector and then inserting the result into the low part of a new 256-bit vector
Definition at line 16097 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and isUndefOrEqual().
Referenced by PerformShuffleCombine256().
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isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the same as extracting the low 128-bit part of 256-bit vector and then inserting the result into the high part of a new 256-bit vector
Definition at line 16113 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), and isUndefOrEqual().
Referenced by PerformShuffleCombine256().
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isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE) correspond consecutively to elements from one of the vector operands, starting from its index OpIdx. Also tell OpNum which source vector operand.
Definition at line 5107 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt().
Referenced by isVectorShiftLeft(), and isVectorShiftRight().
isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to 128/256-bit SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be reverse of what x86 shuffles want.
Definition at line 3720 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), and isUndefOrInRange().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal(), and llvm::X86TargetLowering::isVectorClearMaskLegal().
isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are all the same.
Definition at line 4673 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().
Referenced by LowerScalarImmediateShift(), LowerVectorBroadcast(), PerformOrCombine(), PerformSELECTCombine(), performShiftToAllZeros(), PerformSHLCombine(), and WidenMaskArithmetic().
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IsTailCallConvention - Return true if the calling convention is one that supports tail call optimization.
Definition at line 2087 of file X86ISelLowering.cpp.
References llvm::CallingConv::Fast, llvm::CallingConv::GHC, and llvm::CallingConv::HiPE.
Referenced by FuncIsMadeTailCallSafe().
Definition at line 3262 of file X86ISelLowering.cpp.
References llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::PALIGNR, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::SHUFP, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, and llvm::X86ISD::VPERMILP.
Referenced by getShuffleScalarElt(), and XFormVExtractWithShuffleIntoLoad().
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Definition at line 10152 of file X86ISelLowering.cpp.
References llvm::tgtok::Bits, llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SelectionDAG::MaskedValueIsZero(), and llvm::ISD::TRUNCATE.
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isUndefOrEqual - Val is either less than zero (undef) or equal to the specified value.
Definition at line 3544 of file X86ISelLowering.cpp.
Referenced by Compact8x32ShuffleNode(), isCommutedMOVLMask(), isMOVDDUPMask(), isMOVDDUPYMask(), isMOVHLPS_v_undef_Mask(), isMOVHLPSMask(), isMOVLHPSMask(), isMOVLMask(), isMOVLPMask(), isMOVSHDUPMask(), isMOVSLDUPMask(), isPALIGNRMask(), isSequentialOrUndefInRange(), isShuffleHigh128VectorInsertLow(), isShuffleLow128VectorInsertHigh(), isUNPCKH_v_undef_Mask(), isUNPCKHMask(), isUNPCKL_v_undef_Mask(), isUNPCKLMask(), isVPERMILPMask(), PerformShuffleCombine256(), ShouldXformToMOVHLPS(), and ShouldXformToMOVLP().
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isUndefOrInRange - Return true if Val is undef or if its value falls within the specified range (L, H].
Definition at line 3538 of file X86ISelLowering.cpp.
References llvm::HexagonISD::Hi.
Referenced by isCommutedMOVLMask(), isPALIGNRMask(), isPermImmMask(), isPSHUFHWMask(), isPSHUFLWMask(), isSHUFPMask(), and isVPERMILPMask().
isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, <2, 2, 3, 3>
Definition at line 4045 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
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isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKH.
Definition at line 3954 of file X86ISelLowering.cpp.
References llvm::MVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, <0, 0, 1, 1>
Definition at line 4002 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
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isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to UNPCKL.
Definition at line 3906 of file X86ISelLowering.cpp.
References llvm::MVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and isUndefOrEqual().
Referenced by llvm::X86TargetLowering::isShuffleMaskLegal().
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isVectorShift - Returns true if the shuffle can be implemented as a logical left or right shift of a vector.
Definition at line 5205 of file X86ISelLowering.cpp.
References llvm::SDNode::getSimpleValueType(), llvm::MVT::is128BitVector(), isVectorShiftLeft(), and isVectorShiftRight().
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isVectorShiftLeft - Returns true if the shuffle can be implemented as a logical left shift of a vector.
Definition at line 5170 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), getNumOfConsecutiveZeros(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), and isShuffleMaskConsecutive().
Referenced by isVectorShift().
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isVectorShiftRight - Returns true if the shuffle can be implemented as a logical left shift of a vector.
Definition at line 5135 of file X86ISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), getNumOfConsecutiveZeros(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), and isShuffleMaskConsecutive().
Referenced by isVectorShift().
isVEXTRACTIndex - Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable for instruction that extract 128 or 256 bit vectors
Definition at line 4342 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), and llvm::MVT::getVectorElementType().
Referenced by llvm::X86::isVEXTRACT128Index(), and llvm::X86::isVEXTRACT256Index().
isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable for input to insertion of 128 or 256-bit subvectors
Definition at line 4361 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), and llvm::MVT::getVectorElementType().
Referenced by llvm::X86::isVINSERT128Index(), and llvm::X86::isVINSERT256Index().
isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered as permutations between 128-bit chunks or halves. As an example: this shuffle bellow: vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> The first half comes from the second half of V1 and the second half from the the second half of V2.
Definition at line 4103 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), and isSequentialOrUndefInRange().
isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand specifies a shuffle of elements that is suitable for input to VPERMILPD*. Note that VPERMIL mask matching is different depending whether theunderlying type is 32 or 64. In the VPERMILPS the high half of the mask should point to the same elements of the low, but to the higher half of the source. In VPERMILPD the two lanes could be shuffled independently of each other with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
Definition at line 4201 of file X86ISelLowering.cpp.
References llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), isUndefOrEqual(), and isUndefOrInRange().
Definition at line 10122 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::AND, llvm::X86ISD::CMP, llvm::X86ISD::COMI, llvm::X86ISD::DEC, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getResNo(), llvm::X86ISD::INC, llvm::X86ISD::OR, llvm::X86ISD::SAHF, llvm::X86ISD::SBB, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::UCOMI, llvm::X86ISD::UMUL, and llvm::X86ISD::XOR.
Definition at line 10471 of file X86ISelLowering.cpp.
References llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::X86ISD::SETCC, and llvm::ISD::XOR.
Definition at line 10147 of file X86ISelLowering.cpp.
References llvm::dyn_cast(), and llvm::ConstantSDNode::isNullValue().
Referenced by PerformAndCombine().
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isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved to an zero vector. FIXME: move to dag combiner / method on ShuffleVectorSDNode
Definition at line 4687 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorAllZeros(), llvm::X86::isZeroNode(), llvm::ISD::UNDEF, and llvm::NVPTX::PTXLdStInstCode::V2.
Referenced by NormalizeVectorShuffle().
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Definition at line 12390 of file X86ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::EVT::is256BitVector(), and llvm::EVT::isInteger().
Referenced by LowerADD(), LowerMUL(), and LowerSUB().
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Definition at line 9804 of file X86ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::is256BitVector(), and llvm::ISD::SETCC.
Referenced by LowerVSETCC().
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Definition at line 12417 of file X86ISelLowering.cpp.
References llvm::SDValue::getValueType(), llvm::EVT::is256BitVector(), llvm::EVT::isInteger(), and Lower256IntArith().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 13296 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::X86ISD::SBB, llvm::X86ISD::SUB, llvm::ISD::SUBC, and llvm::ISD::SUBE.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 12086 of file X86ISelLowering.cpp.
References llvm::SDValue::getOperand().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 8944 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::X86Subtarget::hasFp256(), and LowerAVXExtend().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 5315 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::i32, llvm::SelectionDAG::InferPtrAlignment(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::ISD::isNormalLoad(), llvm::A64DB::LD, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::MachineFrameInfo::setObjectAlignment().
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Definition at line 13147 of file X86ISelLowering.cpp.
References llvm::CrossThread, llvm::N86::ESP, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::X86ISD::MEMBARRIER, llvm::X86ISD::MFENCE, llvm::MVT::Other, and llvm::SequentiallyConsistent.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 13271 of file X86ISelLowering.cpp.
References llvm::ISD::ATOMIC_SWAP, llvm::SelectionDAG::getAtomic(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::SequentiallyConsistent.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 6140 of file X86ISelLowering.cpp.
References Concat128BitVectors(), Concat256BitVectors(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), and llvm::NVPTX::PTXLdStInstCode::V2.
Referenced by LowerCONCAT_VECTORS().
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Definition at line 8870 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), getUnpackh(), getUnpackl(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getZeroVector(), llvm::X86Subtarget::hasInt256(), llvm::RegState::Undef, llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::X86ISD::VZEXT_MOVL, and llvm::ISD::ZERO_EXTEND.
Referenced by LowerANY_EXTEND(), and LowerZERO_EXTEND().
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Definition at line 13234 of file X86ISelLowering.cpp.
References llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), and llvm::MVT::isVector().
Referenced by llvm::X86TargetLowering::LowerOperation().
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LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
Definition at line 5221 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), getZeroVector(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::OR, llvm::ISD::SHL, llvm::MVT::v16i8, llvm::MVT::v8i16, and llvm::ISD::ZERO_EXTEND.
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LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
Definition at line 5269 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), getZeroVector(), llvm::ISD::INSERT_VECTOR_ELT, and llvm::MVT::v8i16.
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Definition at line 13183 of file X86ISelLowering.cpp.
References llvm::A64CC::AL, llvm::array_lengthof(), llvm::N86::EAX, llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getOperand(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::X86ISD::LCMPXCHG_DAG, llvm_unreachable, llvm::MVT::Other, llvm::MVT::SimpleTy, and T.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 6156 of file X86ISelLowering.cpp.
References llvm::SDValue::getNumOperands(), and LowerAVXCONCAT_VECTORS().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 12309 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::X86ISD::BSR, llvm::X86ISD::CMOV, llvm::X86::COND_E, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i8, llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 12343 of file X86ISelLowering.cpp.
References llvm::X86ISD::BSR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i8, llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 12368 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::X86ISD::BSF, llvm::X86ISD::CMOV, llvm::X86::COND_E, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, and llvm::MVT::i8.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 7880 of file X86ISelLowering.cpp.
References Extract128BitVector(), Extract256BitVector(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::X86Subtarget::hasFp256(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and llvm::MVT::is512BitVector().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 7575 of file X86ISelLowering.cpp.
References Assert, llvm::ISD::AssertZext, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::is128BitVector(), llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::ISD::STORE, llvm::ISD::TRUNCATE, llvm::SDNode::use_begin(), and llvm::MVT::v4i32.
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Definition at line 9322 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::X86ISD::FGETSIGNx86, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), and llvm::SDValue::getSimpleValueType().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 9161 of file X86ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::v2f32, llvm::MVT::v4f32, and llvm::X86ISD::VFPEXT.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 13322 of file X86ISelLowering.cpp.
References llvm::CallingConv::C, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::StructType::get(), llvm::VectorType::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExternalSymbol(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::X86Subtarget::is64Bit(), llvm::TargetLowering::ArgListEntry::isSExt, llvm::X86Subtarget::isTargetDarwin(), llvm::TargetLowering::ArgListEntry::isZExt, llvm::TargetLowering::LowerCallTo(), llvm::ISD::MERGE_VALUES, llvm::TargetLowering::ArgListEntry::Node, and llvm::TargetLowering::ArgListEntry::Ty.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 7906 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::X86Subtarget::hasFp256(), Insert128BitVector(), Insert256BitVector(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and llvm::MVT::is512BitVector().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 7747 of file X86ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::MVT::f32, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86ISD::INSERTPS, llvm::MVT::is128BitVector(), llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::ISD::SCALAR_TO_VECTOR, llvm::MVT::v16i8, llvm::MVT::v4f32, and llvm::MVT::v8i16.
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Definition at line 11802 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::array_lengthof(), llvm::X86ISD::CMOV, llvm::X86::COND_B, llvm::X86::COND_NE, llvm::N86::EBP, llvm::N86::ECX, llvm::X86ISD::EH_RETURN, llvm::X86ISD::EH_SJLJ_LONGJMP, llvm::X86ISD::EH_SJLJ_SETJMP, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::MachineFunction::getFrameInfo(), llvm::X86RegisterInfo::getFrameRegister(), getGatherNode(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), getMGatherNode(), getMScatterNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::TargetMachine::getRegisterInfo(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getScatterNode(), llvm::X86RegisterInfo::getSlotSize(), llvm::SelectionDAG::getStore(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SDNode::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::Glue, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, llvm::ISD::MERGE_VALUES, llvm::MVT::Other, llvm::X86ISD::RDRAND, llvm::X86ISD::RDSEED, llvm::AArch64ISD::Ret, llvm::X86ISD::SETCC, llvm::MachineFrameInfo::setFrameAddressIsTaken(), llvm::MachineFrameInfo::setReturnAddressIsTaken(), llvm::Intrinsic::x86_avx512_gather_dpd_512, llvm::Intrinsic::x86_avx512_gather_dpd_mask_512, llvm::Intrinsic::x86_avx512_gather_dpi_512, llvm::Intrinsic::x86_avx512_gather_dpi_mask_512, llvm::Intrinsic::x86_avx512_gather_dpq_512, llvm::Intrinsic::x86_avx512_gather_dpq_mask_512, llvm::Intrinsic::x86_avx512_gather_dps_512, llvm::Intrinsic::x86_avx512_gather_dps_mask_512, llvm::Intrinsic::x86_avx512_gather_qpd_512, llvm::Intrinsic::x86_avx512_gather_qpd_mask_512, llvm::Intrinsic::x86_avx512_gather_qpi_512, llvm::Intrinsic::x86_avx512_gather_qpi_mask_512, llvm::Intrinsic::x86_avx512_gather_qpq_512, llvm::Intrinsic::x86_avx512_gather_qpq_mask_512, llvm::Intrinsic::x86_avx512_gather_qps_512, llvm::Intrinsic::x86_avx512_gather_qps_mask_512, llvm::Intrinsic::x86_avx512_scatter_dpd_512, llvm::Intrinsic::x86_avx512_scatter_dpd_mask_512, llvm::Intrinsic::x86_avx512_scatter_dpi_512, llvm::Intrinsic::x86_avx512_scatter_dpi_mask_512, llvm::Intrinsic::x86_avx512_scatter_dpq_512, llvm::Intrinsic::x86_avx512_scatter_dpq_mask_512, llvm::Intrinsic::x86_avx512_scatter_dps_512, llvm::Intrinsic::x86_avx512_scatter_dps_mask_512, llvm::Intrinsic::x86_avx512_scatter_qpd_512, llvm::Intrinsic::x86_avx512_scatter_qpd_mask_512, llvm::Intrinsic::x86_avx512_scatter_qpi_512, llvm::Intrinsic::x86_avx512_scatter_qpi_mask_512, llvm::Intrinsic::x86_avx512_scatter_qpq_512, llvm::Intrinsic::x86_avx512_scatter_qpq_mask_512, llvm::Intrinsic::x86_avx512_scatter_qps_512, llvm::Intrinsic::x86_avx512_scatter_qps_mask_512, llvm::Intrinsic::x86_rdrand_16, llvm::Intrinsic::x86_rdrand_32, llvm::Intrinsic::x86_rdrand_64, llvm::Intrinsic::x86_rdseed_16, llvm::Intrinsic::x86_rdseed_32, llvm::Intrinsic::x86_rdseed_64, llvm::Intrinsic::x86_xtest, llvm::X86ISD::XTEST, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 11022 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::X86ISD::COMI, llvm::X86::COND_A, llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_INVALID, llvm::X86::COND_O, llvm::X86::COND_S, llvm::SmallVectorTemplateCommon< T >::data(), llvm::X86ISD::FHADD, llvm::X86ISD::FHSUB, llvm::X86ISD::FMADD, llvm::X86ISD::FMADDSUB, llvm::X86ISD::FMAX, llvm::X86ISD::FMIN, llvm::X86ISD::FMSUB, llvm::X86ISD::FMSUBADD, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMSUB, llvm::ISD::FSQRT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getTargetVShiftNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::X86ISD::HADD, llvm::X86ISD::HSUB, llvm::MVT::i32, llvm::MVT::i8, llvm::X86ISD::INSERTPS, llvm::X86ISD::KORTEST, llvm_unreachable, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::X86ISD::PCMPESTRI, llvm::X86ISD::PCMPISTRI, llvm::X86ISD::PMULUDQ, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSIGN, llvm::X86ISD::PTEST, llvm::X86ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::X86ISD::SMAX, llvm::X86ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SRL, llvm::X86ISD::SUBUS, llvm::X86ISD::TESTP, TranslateX86CC(), llvm::X86ISD::UCOMI, llvm::X86ISD::UMAX, llvm::X86ISD::UMIN, llvm::MVT::v16i1, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMV, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLI, llvm::Intrinsic::x86_avx2_permd, llvm::Intrinsic::x86_avx2_permps, llvm::Intrinsic::x86_avx2_phadd_d, llvm::Intrinsic::x86_avx2_phadd_w, llvm::Intrinsic::x86_avx2_phsub_d, llvm::Intrinsic::x86_avx2_phsub_w, llvm::Intrinsic::x86_avx2_pmaxs_b, llvm::Intrinsic::x86_avx2_pmaxs_d, llvm::Intrinsic::x86_avx2_pmaxs_w, llvm::Intrinsic::x86_avx2_pmaxu_b, llvm::Intrinsic::x86_avx2_pmaxu_d, llvm::Intrinsic::x86_avx2_pmaxu_w, llvm::Intrinsic::x86_avx2_pmins_b, llvm::Intrinsic::x86_avx2_pmins_d, llvm::Intrinsic::x86_avx2_pmins_w, llvm::Intrinsic::x86_avx2_pminu_b, llvm::Intrinsic::x86_avx2_pminu_d, llvm::Intrinsic::x86_avx2_pminu_w, llvm::Intrinsic::x86_avx2_pmulu_dq, llvm::Intrinsic::x86_avx2_pshuf_b, llvm::Intrinsic::x86_avx2_psign_b, llvm::Intrinsic::x86_avx2_psign_d, llvm::Intrinsic::x86_avx2_psign_w, llvm::Intrinsic::x86_avx2_psll_d, llvm::Intrinsic::x86_avx2_psll_q, llvm::Intrinsic::x86_avx2_psll_w, llvm::Intrinsic::x86_avx2_pslli_d, llvm::Intrinsic::x86_avx2_pslli_q, llvm::Intrinsic::x86_avx2_pslli_w, llvm::Intrinsic::x86_avx2_psllv_d, llvm::Intrinsic::x86_avx2_psllv_d_256, llvm::Intrinsic::x86_avx2_psllv_q, llvm::Intrinsic::x86_avx2_psllv_q_256, llvm::Intrinsic::x86_avx2_psra_d, llvm::Intrinsic::x86_avx2_psra_w, llvm::Intrinsic::x86_avx2_psrai_d, llvm::Intrinsic::x86_avx2_psrai_w, llvm::Intrinsic::x86_avx2_psrav_d, llvm::Intrinsic::x86_avx2_psrav_d_256, llvm::Intrinsic::x86_avx2_psrl_d, llvm::Intrinsic::x86_avx2_psrl_q, llvm::Intrinsic::x86_avx2_psrl_w, llvm::Intrinsic::x86_avx2_psrli_d, llvm::Intrinsic::x86_avx2_psrli_q, llvm::Intrinsic::x86_avx2_psrli_w, llvm::Intrinsic::x86_avx2_psrlv_d, llvm::Intrinsic::x86_avx2_psrlv_d_256, llvm::Intrinsic::x86_avx2_psrlv_q, llvm::Intrinsic::x86_avx2_psrlv_q_256, llvm::Intrinsic::x86_avx2_psubus_b, llvm::Intrinsic::x86_avx2_psubus_w, llvm::Intrinsic::x86_avx2_vperm2i128, llvm::Intrinsic::x86_avx512_kortestc, llvm::Intrinsic::x86_avx512_kortestz, llvm::Intrinsic::x86_avx512_max_pd_512, llvm::Intrinsic::x86_avx512_max_ps_512, llvm::Intrinsic::x86_avx512_min_pd_512, llvm::Intrinsic::x86_avx512_min_ps_512, llvm::Intrinsic::x86_avx512_pmaxs_d, llvm::Intrinsic::x86_avx512_pmaxs_q, llvm::Intrinsic::x86_avx512_pmaxu_d, llvm::Intrinsic::x86_avx512_pmaxu_q, llvm::Intrinsic::x86_avx512_pmins_d, llvm::Intrinsic::x86_avx512_pmins_q, llvm::Intrinsic::x86_avx512_pminu_d, llvm::Intrinsic::x86_avx512_pminu_q, llvm::Intrinsic::x86_avx_hadd_pd_256, llvm::Intrinsic::x86_avx_hadd_ps_256, llvm::Intrinsic::x86_avx_hsub_pd_256, llvm::Intrinsic::x86_avx_hsub_ps_256, llvm::Intrinsic::x86_avx_max_pd_256, llvm::Intrinsic::x86_avx_max_ps_256, llvm::Intrinsic::x86_avx_min_pd_256, llvm::Intrinsic::x86_avx_min_ps_256, llvm::Intrinsic::x86_avx_ptestc_256, llvm::Intrinsic::x86_avx_ptestnzc_256, llvm::Intrinsic::x86_avx_ptestz_256, llvm::Intrinsic::x86_avx_sqrt_pd_256, llvm::Intrinsic::x86_avx_sqrt_ps_256, llvm::Intrinsic::x86_avx_vperm2f128_pd_256, llvm::Intrinsic::x86_avx_vperm2f128_ps_256, llvm::Intrinsic::x86_avx_vperm2f128_si_256, llvm::Intrinsic::x86_avx_vtestc_pd, llvm::Intrinsic::x86_avx_vtestc_pd_256, llvm::Intrinsic::x86_avx_vtestc_ps, llvm::Intrinsic::x86_avx_vtestc_ps_256, llvm::Intrinsic::x86_avx_vtestnzc_pd, llvm::Intrinsic::x86_avx_vtestnzc_pd_256, llvm::Intrinsic::x86_avx_vtestnzc_ps, llvm::Intrinsic::x86_avx_vtestnzc_ps_256, llvm::Intrinsic::x86_avx_vtestz_pd, llvm::Intrinsic::x86_avx_vtestz_pd_256, llvm::Intrinsic::x86_avx_vtestz_ps, llvm::Intrinsic::x86_avx_vtestz_ps_256, llvm::Intrinsic::x86_fma_vfmadd_pd, llvm::Intrinsic::x86_fma_vfmadd_pd_256, llvm::Intrinsic::x86_fma_vfmadd_pd_512, llvm::Intrinsic::x86_fma_vfmadd_ps, llvm::Intrinsic::x86_fma_vfmadd_ps_256, llvm::Intrinsic::x86_fma_vfmadd_ps_512, llvm::Intrinsic::x86_fma_vfmaddsub_pd, llvm::Intrinsic::x86_fma_vfmaddsub_pd_256, llvm::Intrinsic::x86_fma_vfmaddsub_pd_512, llvm::Intrinsic::x86_fma_vfmaddsub_ps, llvm::Intrinsic::x86_fma_vfmaddsub_ps_256, llvm::Intrinsic::x86_fma_vfmaddsub_ps_512, llvm::Intrinsic::x86_fma_vfmsub_pd, llvm::Intrinsic::x86_fma_vfmsub_pd_256, llvm::Intrinsic::x86_fma_vfmsub_pd_512, llvm::Intrinsic::x86_fma_vfmsub_ps, llvm::Intrinsic::x86_fma_vfmsub_ps_256, llvm::Intrinsic::x86_fma_vfmsub_ps_512, llvm::Intrinsic::x86_fma_vfmsubadd_pd, llvm::Intrinsic::x86_fma_vfmsubadd_pd_256, llvm::Intrinsic::x86_fma_vfmsubadd_pd_512, llvm::Intrinsic::x86_fma_vfmsubadd_ps, llvm::Intrinsic::x86_fma_vfmsubadd_ps_256, llvm::Intrinsic::x86_fma_vfmsubadd_ps_512, llvm::Intrinsic::x86_fma_vfnmadd_pd, llvm::Intrinsic::x86_fma_vfnmadd_pd_256, llvm::Intrinsic::x86_fma_vfnmadd_pd_512, llvm::Intrinsic::x86_fma_vfnmadd_ps, llvm::Intrinsic::x86_fma_vfnmadd_ps_256, llvm::Intrinsic::x86_fma_vfnmadd_ps_512, llvm::Intrinsic::x86_fma_vfnmsub_pd, llvm::Intrinsic::x86_fma_vfnmsub_pd_256, llvm::Intrinsic::x86_fma_vfnmsub_pd_512, llvm::Intrinsic::x86_fma_vfnmsub_ps, llvm::Intrinsic::x86_fma_vfnmsub_ps_256, llvm::Intrinsic::x86_fma_vfnmsub_ps_512, llvm::Intrinsic::x86_sse2_comieq_sd, llvm::Intrinsic::x86_sse2_comige_sd, llvm::Intrinsic::x86_sse2_comigt_sd, llvm::Intrinsic::x86_sse2_comile_sd, llvm::Intrinsic::x86_sse2_comilt_sd, llvm::Intrinsic::x86_sse2_comineq_sd, llvm::Intrinsic::x86_sse2_max_pd, llvm::Intrinsic::x86_sse2_min_pd, llvm::Intrinsic::x86_sse2_pmaxs_w, llvm::Intrinsic::x86_sse2_pmaxu_b, llvm::Intrinsic::x86_sse2_pmins_w, llvm::Intrinsic::x86_sse2_pminu_b, llvm::Intrinsic::x86_sse2_pmulu_dq, llvm::Intrinsic::x86_sse2_psll_d, llvm::Intrinsic::x86_sse2_psll_q, llvm::Intrinsic::x86_sse2_psll_w, llvm::Intrinsic::x86_sse2_pslli_d, llvm::Intrinsic::x86_sse2_pslli_q, llvm::Intrinsic::x86_sse2_pslli_w, llvm::Intrinsic::x86_sse2_psra_d, llvm::Intrinsic::x86_sse2_psra_w, llvm::Intrinsic::x86_sse2_psrai_d, llvm::Intrinsic::x86_sse2_psrai_w, llvm::Intrinsic::x86_sse2_psrl_d, llvm::Intrinsic::x86_sse2_psrl_q, llvm::Intrinsic::x86_sse2_psrl_w, llvm::Intrinsic::x86_sse2_psrli_d, llvm::Intrinsic::x86_sse2_psrli_q, llvm::Intrinsic::x86_sse2_psrli_w, llvm::Intrinsic::x86_sse2_psubus_b, llvm::Intrinsic::x86_sse2_psubus_w, llvm::Intrinsic::x86_sse2_sqrt_pd, llvm::Intrinsic::x86_sse2_ucomieq_sd, llvm::Intrinsic::x86_sse2_ucomige_sd, llvm::Intrinsic::x86_sse2_ucomigt_sd, llvm::Intrinsic::x86_sse2_ucomile_sd, llvm::Intrinsic::x86_sse2_ucomilt_sd, llvm::Intrinsic::x86_sse2_ucomineq_sd, llvm::Intrinsic::x86_sse3_hadd_pd, llvm::Intrinsic::x86_sse3_hadd_ps, llvm::Intrinsic::x86_sse3_hsub_pd, llvm::Intrinsic::x86_sse3_hsub_ps, llvm::Intrinsic::x86_sse41_insertps, llvm::Intrinsic::x86_sse41_pmaxsb, llvm::Intrinsic::x86_sse41_pmaxsd, llvm::Intrinsic::x86_sse41_pmaxud, llvm::Intrinsic::x86_sse41_pmaxuw, llvm::Intrinsic::x86_sse41_pminsb, llvm::Intrinsic::x86_sse41_pminsd, llvm::Intrinsic::x86_sse41_pminud, llvm::Intrinsic::x86_sse41_pminuw, llvm::Intrinsic::x86_sse41_ptestc, llvm::Intrinsic::x86_sse41_ptestnzc, llvm::Intrinsic::x86_sse41_ptestz, llvm::Intrinsic::x86_sse42_pcmpestri128, llvm::Intrinsic::x86_sse42_pcmpestria128, llvm::Intrinsic::x86_sse42_pcmpestric128, llvm::Intrinsic::x86_sse42_pcmpestrio128, llvm::Intrinsic::x86_sse42_pcmpestris128, llvm::Intrinsic::x86_sse42_pcmpestriz128, llvm::Intrinsic::x86_sse42_pcmpistri128, llvm::Intrinsic::x86_sse42_pcmpistria128, llvm::Intrinsic::x86_sse42_pcmpistric128, llvm::Intrinsic::x86_sse42_pcmpistrio128, llvm::Intrinsic::x86_sse42_pcmpistris128, llvm::Intrinsic::x86_sse42_pcmpistriz128, llvm::Intrinsic::x86_sse_comieq_ss, llvm::Intrinsic::x86_sse_comige_ss, llvm::Intrinsic::x86_sse_comigt_ss, llvm::Intrinsic::x86_sse_comile_ss, llvm::Intrinsic::x86_sse_comilt_ss, llvm::Intrinsic::x86_sse_comineq_ss, llvm::Intrinsic::x86_sse_max_ps, llvm::Intrinsic::x86_sse_min_ps, llvm::Intrinsic::x86_sse_sqrt_ps, llvm::Intrinsic::x86_sse_ucomieq_ss, llvm::Intrinsic::x86_sse_ucomige_ss, llvm::Intrinsic::x86_sse_ucomigt_ss, llvm::Intrinsic::x86_sse_ucomile_ss, llvm::Intrinsic::x86_sse_ucomilt_ss, llvm::Intrinsic::x86_sse_ucomineq_ss, llvm::Intrinsic::x86_ssse3_phadd_d_128, llvm::Intrinsic::x86_ssse3_phadd_w_128, llvm::Intrinsic::x86_ssse3_phsub_d_128, llvm::Intrinsic::x86_ssse3_phsub_w_128, llvm::Intrinsic::x86_ssse3_pshuf_b_128, llvm::Intrinsic::x86_ssse3_psign_b_128, llvm::Intrinsic::x86_ssse3_psign_d_128, llvm::Intrinsic::x86_ssse3_psign_w_128, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 9832 of file X86ISelLowering.cpp.
References llvm::X86ISD::CMPM, llvm::X86ISD::CMPMU, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i1, llvm::MVT::i8, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::NVPTX::PTXLdStInstCode::Unsigned.
Referenced by LowerVSETCC().
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Definition at line 13255 of file X86ISelLowering.cpp.
References llvm::ISD::ATOMIC_LOAD_ADD, llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and llvm::ISD::SUB.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 12431 of file X86ISelLowering.cpp.
References llvm::ARM_PROC::A, llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), getTargetVShiftByConstNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::EVT::is256BitVector(), Lower256IntArith(), llvm::X86ISD::PMULUDQ, llvm::MVT::v16i32, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::X86ISD::VSHLI, and llvm::X86ISD::VSRLI.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 13215 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::ISD::OR, llvm::MVT::Other, llvm::X86ISD::RDTSC_DAG, and llvm::ISD::SHL.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 7849 of file X86ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i32, llvm::MVT::i64, Insert128BitVector(), llvm::MVT::is128BitVector(), llvm::ISD::SCALAR_TO_VECTOR, llvm::MVT::v1i64, and llvm::MVT::v4i32.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 12558 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getTargetVShiftByConstNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getZeroVector(), llvm::ConstantSDNode::getZExtValue(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasInt256(), llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), isSplatVector(), llvm_unreachable, llvm::Log2_32_Ceil(), llvm::X86ISD::PCMPGT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRLI, and llvm::ISD::XOR.
Referenced by LowerShift().
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Definition at line 12730 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSimpleVT(), getTargetVShiftNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasInt256(), llvm::MVT::i32, llvm::ISD::INSERT_VECTOR_ELT, llvm::X86Subtarget::is64Bit(), llvm_unreachable, llvm::ISD::SHL, llvm::MVT::SimpleTy, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::ISD::UNDEF, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::ISD::VECTOR_SHUFFLE, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLI, and llvm::ISD::ZERO_EXTEND.
Referenced by LowerShift().
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Definition at line 12503 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, ADD, llvm::ISD::BUILD_VECTOR, llvm::APInt::countTrailingZeros(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::APInt::isNonNegative(), llvm::APInt::isPowerOf2(), llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 12874 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), getTargetVShiftByConstNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE2(), llvm::EVT::is256BitVector(), LowerScalarImmediateShift(), LowerScalarVariableShift(), llvm::ISD::MUL, llvm::X86ISD::PCMPEQ, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::ISD::VSELECT, and llvm::X86ISD::VSHLI.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 10405 of file X86ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::X86Subtarget::hasInt256(), llvm::MVT::i1, llvm::MVT::is512BitVector(), LowerSIGN_EXTEND_AVX512(), llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::X86ISD::VSEXT_MOVL.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 10374 of file X86ISelLowering.cpp.
References llvm::ConstantInt::get(), llvm::APInt::getAllOnesValue(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i1, llvm::MVT::is512BitVector(), llvm::MVT::v16i32, llvm::MVT::v8i64, llvm::X86ISD::VBROADCASTM, llvm::X86ISD::VSEXT, and llvm::X86ISD::VTRUNC.
Referenced by LowerSIGN_EXTEND().
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Definition at line 12424 of file X86ISelLowering.cpp.
References llvm::SDValue::getValueType(), llvm::EVT::is256BitVector(), llvm::EVT::isInteger(), and Lower256IntArith().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 8223 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::MachinePointerInfo::getGOT(), llvm::Type::getInt8PtrTy(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::Constant::getNullValue(), llvm::GlobalAddressSDNode::getOffset(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDNode::getValueType(), llvm::X86ISD::GlobalBaseReg, llvm::TLSModel::InitialExec, llvm_unreachable, llvm::TLSModel::LocalExec, llvm::X86II::MO_GOTNTPOFF, llvm::X86II::MO_GOTTPOFF, llvm::X86II::MO_INDNTPOFF, llvm::X86II::MO_NTPOFF, llvm::X86II::MO_TPOFF, llvm::MipsISD::ThreadPointer, llvm::X86ISD::Wrapper, and llvm::X86ISD::WrapperRIP.
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Definition at line 8163 of file X86ISelLowering.cpp.
References llvm::N86::EAX, llvm::N86::EBX, llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), GetTLSADDR(), llvm::SDValue::getValue(), llvm::X86ISD::GlobalBaseReg, and llvm::X86II::MO_TLSGD.
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Definition at line 8177 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getEntryNode(), GetTLSADDR(), and llvm::X86II::MO_TLSGD.
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Definition at line 8183 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::N86::EAX, llvm::N86::EBX, llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::GlobalAddressSDNode::getGlobal(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SelectionDAG::getTargetGlobalAddress(), GetTLSADDR(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::X86ISD::GlobalBaseReg, llvm::X86MachineFunctionInfo::incNumLocalDynamicTLSAccesses(), llvm::X86II::MO_DTPOFF, llvm::X86II::MO_TLSLD, llvm::X86II::MO_TLSLDM, and llvm::X86ISD::Wrapper.
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Definition at line 10948 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemcpy(), llvm::SDValue::getOperand(), and llvm::X86Subtarget::is64Bit().
Referenced by llvm::X86TargetLowering::LowerOperation().
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LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 4 elements, and match them with several different shuffle types.
Definition at line 6851 of file X86ISelLowering.cpp.
References CommuteVectorShuffleMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is128BitVector(), std::swap(), and llvm::NVPTX::PTXLdStInstCode::V2.
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LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles which could not be matched by any known target speficic shuffle
Definition at line 6737 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::ISD::BUILD_VECTOR, llvm::SmallVectorImpl< T >::clear(), Compact8x32ShuffleNode(), llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::SmallVectorTemplateCommon< T >::size().
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Definition at line 6166 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::X86ISD::BLENDI, llvm::SelectionDAG::getConstant(), llvm::MVT::getFloatingPointVT(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE41(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::is512BitVector(), llvm::AArch64ISD::Ret, llvm::MVT::v16i16, and llvm::NVPTX::PTXLdStInstCode::V2.
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Definition at line 6484 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SmallVectorImpl< T >::clear(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::X86Subtarget::hasSSSE3(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isBuildVectorAllZeros(), llvm::ShuffleVectorSDNode::isSplat(), llvm::ISD::OR, PromoteSplat(), llvm::X86ISD::PSHUFB, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::UNDEF, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::MVT::v8i16.
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Definition at line 6613 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, CommuteVectorShuffleMask(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::X86Subtarget::hasInt256(), llvm::MVT::i8, llvm::ISD::isBuildVectorAllZeros(), llvm::X86ISD::PSHUFB, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::MVT::v32i8.
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Definition at line 6230 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SmallVectorImpl< T >::clear(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getShufflePSHUFHWImmediate(), getShufflePSHUFLWImmediate(), getTargetShuffleNode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::X86Subtarget::hasSSSE3(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, llvm::ShuffleVectorSDNode::isSplat(), llvm::ISD::OR, PromoteSplat(), llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v2i64, llvm::MVT::v8i16, and llvm::ISD::VECTOR_SHUFFLE.
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Definition at line 9335 of file X86ISelLowering.cpp.
References llvm::SmallVectorTemplateCommon< T >::back(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::begin(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BITCAST, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::end(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::find(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::hasOneUse(), llvm::X86Subtarget::hasSSE41(), I, llvm::MVT::i32, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT >, KeyT, ValueT, KeyInfoT >::insert(), llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::ISD::OR, llvm::MVT::Other, llvm::X86ISD::PTEST, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::MVT::v2i64, and llvm::MVT::v4i64.
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LowerVectorBroadcast - Attempt to use the vbroadcast instruction to generate a splat value for the following cases:
Definition at line 5491 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::ISD::Constant, llvm::ISD::ConstantFP, Extract128BitVector(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), llvm::EVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::ShuffleVectorSDNode::isSplat(), isSplatVector(), llvm::EVT::isVector(), llvm::ISD::SCALAR_TO_VECTOR, llvm::X86ISD::VBROADCAST, and llvm::ISD::VECTOR_SHUFFLE.
Referenced by NormalizeVectorShuffle().
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Definition at line 7108 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::X86Subtarget::hasInt256(), llvm::SDValue::hasOneUse(), llvm::X86Subtarget::hasSSE41(), llvm::MVT::i64, llvm::MVT::is256BitVector(), llvm::MVT::isInteger(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::UNDEF, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::X86ISD::VZEXT.
Referenced by NormalizeVectorShuffle().
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Definition at line 9866 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::X86ISD::CMPM, llvm::X86ISD::CMPP, EQ, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOperand(), llvm::APInt::getSignBit(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::A64CC::GT, llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::X86Subtarget::hasSSE42(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i8, llvm::MVT::is256BitVector(), llvm::EVT::is512BitVector(), llvm::MVT::isFloatingPoint(), llvm_unreachable, Lower256IntVSETCC(), LowerIntVSETCC_AVX512(), llvm::ISD::OR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPEQM, llvm::X86ISD::PCMPGT, llvm::X86ISD::PCMPGTM, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, std::swap(), translateX86FSETCC(), llvm::ISD::TRUNCATE, llvm::X86ISD::UMAX, llvm::X86ISD::UMIN, llvm::MVT::v2i64, llvm::MVT::v4i32, and llvm::ISD::XOR.
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Definition at line 13004 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADD, llvm::X86::COND_B, llvm::X86::COND_O, llvm::X86ISD::DEC, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SDNode::getVTList(), llvm::MVT::i32, llvm::MVT::i8, llvm::X86ISD::INC, llvm::ConstantSDNode::isOne(), llvm_unreachable, llvm::ISD::MERGE_VALUES, llvm::ISD::SADDO, llvm::X86ISD::SETCC, llvm::X86ISD::SMUL, llvm::ISD::SMULO, llvm::ISD::SSUBO, llvm::X86ISD::SUB, llvm::ISD::UADDO, llvm::X86ISD::UMUL, llvm::ISD::UMULO, and llvm::ISD::USUBO.
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 8955 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::X86Subtarget::hasFp256(), llvm::MVT::i1, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::is512BitVector(), LowerAVXExtend(), and LowerZERO_EXTEND_AVX512().
Referenced by llvm::X86TargetLowering::LowerOperation().
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Definition at line 8913 of file X86ISelLowering.cpp.
References llvm::CallingConv::C, llvm::dyn_cast(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i1, llvm::MVT::is512BitVector(), llvm::MVT::v16i32, llvm::MVT::v8i64, llvm::X86ISD::VBROADCASTM, llvm::X86ISD::VTRUNC, and llvm::X86ISD::VZEXT.
Referenced by LowerZERO_EXTEND().
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MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.
Definition at line 2992 of file X86ISelLowering.cpp.
References llvm::ISD::CopyFromReg, llvm::tgtok::Def, llvm::dyn_cast(), llvm::ISD::FrameIndex, llvm::ISD::ArgFlagsTy::getByValSize(), llvm::MachineOperand::getIndex(), llvm::FrameIndexSDNode::getIndex(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::SDValue::getOperand(), llvm::MachineInstr::getOperand(), getReg(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::MachineOperand::isFI(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::X86InstrInfo::isLoadFromStackSlot(), and llvm::TargetRegisterInfo::isVirtualRegister().
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Matches a VSELECT onto min/max or return 0 if the node doesn't match.
Definition at line 16498 of file X86ISelLowering.cpp.
References llvm::SDValue::getOperand(), llvm::EVT::getSimpleVT(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::SelectionDAG::isEqualTo(), llvm::EVT::isVector(), llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::MVT::SimpleTy, llvm::X86ISD::SMAX, llvm::X86ISD::SMIN, llvm::X86ISD::UMAX, llvm::X86ISD::UMIN, llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v32i8, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MVT::v8i32.
Referenced by PerformSELECTCombine().
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Definition at line 18863 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::X86::COND_B, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i8, and llvm::X86ISD::SETCC_CARRY.
Referenced by PerformSETCCCombine().
Definition at line 3258 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalStore(), and llvm::SDNode::use_begin().
Referenced by getMOVLP(), and llvm::X86TargetLowering::IsDesirableToPromoteOp().
Definition at line 3254 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::hasOneUse(), and llvm::ISD::isNormalLoad().
Referenced by llvm::X86TargetLowering::IsDesirableToPromoteOp(), and MayFoldVectorLoad().
Definition at line 6990 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), MayFoldLoad(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::ISD::UNDEF.
Referenced by getMOVLP().
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NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements that point to V2 points to its first element.
Definition at line 4783 of file X86ISelLowering.cpp.
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Definition at line 7196 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), getVZextMovL(), getZeroVector(), llvm::X86Subtarget::hasSSE2(), llvm::ISD::isBuildVectorAllZeros(), isCommutedMOVLMask(), isMOVLMask(), llvm::ShuffleVectorSDNode::isSplat(), isZeroShuffle(), LowerVectorBroadcast(), LowerVectorIntExtend(), RewriteAsNarrowerShuffle(), llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::MVT::v8i16.
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Definition at line 18996 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::X86ISD::CMP, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MipsISD::Ext, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::X86::isZeroNode(), llvm::X86ISD::SBB, llvm::X86ISD::SETCC, llvm::ISD::SUB, and llvm::ISD::ZERO_EXTEND.
Referenced by PerformAddCombine(), and PerformSubCombine().
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Definition at line 18968 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::X86::COND_B, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::i8, llvm::X86::isZeroNode(), llvm::X86ISD::SETCC_CARRY, and llvm::SDValue::use_empty().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformADDCombine - Do target-specific dag combines on integer adds.
Definition at line 19033 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::X86ISD::HADD, llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSSE3(), isHorizontalBinOp(), OptimizeConditionalInDecrement(), llvm::MVT::v16i16, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MVT::v8i32.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 17684 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::X86ISD::ANDNP, llvm::X86ISD::BEXTR, llvm::X86ISD::BLSI, llvm::X86ISD::BLSR, llvm::X86ISD::BZHI, CanFoldXORWithAllOnes(), CMPEQCombine(), llvm::CountPopulation_64(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::X86Subtarget::hasBMI(), llvm::X86Subtarget::hasBMI2(), llvm::X86Subtarget::hasTBM(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, isAllOnes(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isMask_64(), isZero(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::MVT::v2i64, llvm::MVT::v4i64, and llvm::ISD::XOR.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18915 of file X86ISelLowering.cpp.
References llvm::X86ISD::BRCOND, checkBoolTestSetCCCombine(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getVTList(), and llvm::MVT::i8.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18673 of file X86ISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::APInt::getLowBitsSet(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and llvm::Log2_32().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL].
Definition at line 17166 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::array_lengthof(), llvm::X86ISD::BSF, llvm::X86ISD::BSR, checkBoolTestSetCCCombine(), llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MVT::f80, llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::X86::GetOppositeBranchCondition(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), hasFPCMov(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::SelectionDAG::isKnownNeverZero(), llvm::ISD::MUL, llvm::X86ISD::SETCC, llvm::ISD::SHL, llvm::X86ISD::SUB, std::swap(), llvm::SDValue::use_empty(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index generation and convert it from being a bunch of shuffles and extracts to a simple store and scalar loads to extract the elements.
Definition at line 16398 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SmallVectorTemplateCommon< T >::begin(), llvm::ISD::BITCAST, llvm::SelectionDAG::CreateStackTemporary(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::ISD::EXTRACT_VECTOR_ELT, ExtractBitFromMaskVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MVT::i1, llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::X86ISD::MMX_MOVD2W, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::MVT::v4i32, llvm::MVT::x86mmx, XFormVExtractWithShuffleIntoLoad(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformFADDCombine - Do target-specific dag combines on floating point adds.
Definition at line 18581 of file X86ISelLowering.cpp.
References llvm::X86ISD::FHADD, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasSSE3(), isHorizontalBinOp(), llvm::MVT::v2f64, llvm::MVT::v4f32, llvm::MVT::v4f64, and llvm::MVT::v8f32.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
Definition at line 18648 of file X86ISelLowering.cpp.
References llvm::SDNode::getOperand().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes.
Definition at line 18661 of file X86ISelLowering.cpp.
References llvm::SDNode::getOperand().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18759 of file X86ISelLowering.cpp.
References llvm::ARM_PROC::A, llvm::MVT::f32, llvm::MVT::f64, llvm::X86ISD::FMADD, llvm::X86ISD::FMSUB, llvm::ISD::FNEG, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasFMA(), llvm::X86Subtarget::hasFMA4(), and llvm::TargetLoweringBase::isTypeLegal().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
Definition at line 18627 of file X86ISelLowering.cpp.
References llvm::X86ISD::FMAX, llvm::X86ISD::FMAXC, llvm::X86ISD::FMIN, llvm::X86ISD::FMINC, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTarget(), llvm::SDNode::getValueType(), llvm_unreachable, llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
Definition at line 18612 of file X86ISelLowering.cpp.
References llvm::X86ISD::FOR, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), and llvm::SDNode::getOperand().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformFSUBCombine - Do target-specific dag combines on floating point subs.
Definition at line 18596 of file X86ISelLowering.cpp.
References llvm::X86ISD::FHSUB, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasSSE3(), isHorizontalBinOp(), llvm::MVT::v2f64, llvm::MVT::v4f32, llvm::MVT::v4f64, and llvm::MVT::v8f32.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 17952 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::array_lengthof(), llvm::X86ISD::CMOV, llvm::X86::COND_GE, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::ISD::SRA, llvm::X86ISD::SUB, and llvm::ISD::XOR.
Referenced by PerformXorCombine().
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Definition at line 18836 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::SETEQ, llvm::ISD::SETNE, and llvm::ISD::SUB.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
Definition at line 18026 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::MipsISD::Ext, llvm::ISD::EXTLOAD, llvm::MVT::f64, llvm::MVT::FIRST_INTEGER_VALUETYPE, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::MVT::i8, Insert128BitVector(), llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::MemSDNode::isInvariant(), llvm::MemSDNode::isNonTemporal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::MVT::LAST_INTEGER_VALUETYPE, N, llvm::ISD::NON_EXTLOAD, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SEXTLOAD, llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::SRA, llvm::ISD::TokenFactor, and llvm::X86ISD::VSEXT.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformMulCombine - Optimize a single multiply with constant into two in order to implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
Definition at line 17342 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::MVT::i64, llvm::MVT::i8, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::X86ISD::MUL_IMM, llvm::ISD::SHL, std::swap(), and llvm::SDNode::use_begin().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 17799 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::X86ISD::ANDNP, llvm::ISD::BITCAST, llvm::tgtok::Bits, CMPEQCombine(), llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::ConstantSDNode::getZExtValue(), llvm::X86Subtarget::hasInt256(), llvm::SDValue::hasOneUse(), llvm::X86Subtarget::hasSSE41(), llvm::X86Subtarget::hasSSSE3(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isBuildVectorAllZeros(), isSplatVector(), llvm::X86ISD::PSIGN, llvm::ISD::SHL, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::MVT::v16i8, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4i64, llvm::ISD::VSELECT, llvm::X86ISD::VSRAI, llvm::X, and Y.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT nodes.
Definition at line 16573 of file X86ISelLowering.cpp.
References llvm::ARM_PROC::A, llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::AND, llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::MVT::f32, llvm::MVT::f80, llvm::X86ISD::FMAX, llvm::X86ISD::FMIN, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getContext(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::SelectionDAG::isEqualTo(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::SelectionDAG::isKnownNeverZero(), llvm::TargetLoweringBase::isOperationLegal(), llvm::APInt::isSignBit(), isSplatVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), matchIntegerMINMAX(), llvm::ISD::MUL, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::AArch64ISD::Ret, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::TargetLowering::SimplifyDemandedBits(), llvm::ISD::SUB, llvm::X86ISD::SUBUS, std::swap(), llvm::TargetOptions::UnsafeFPMath, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v32i8, llvm::MVT::v8i16, llvm::ISD::VSELECT, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18871 of file X86ISelLowering.cpp.
References checkBoolTestSetCCCombine(), llvm::X86::COND_A, llvm::X86::COND_B, llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getVTList(), llvm::MVT::i8, MaterializeSETB(), llvm::X86ISD::SETCC, and llvm::X86ISD::SUB.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18740 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasFp256(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isVector(), and WidenMaskArithmetic().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformShiftCombine - Combine shifts.
Definition at line 17478 of file X86ISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), performShiftToAllZeros(), PerformSHLCombine(), llvm::ISD::SHL, and llvm::ISD::SRA.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Returns a vector of 0s if the node in input is a vector logical shift by a constant amount which is known to be bigger than or equal to the vector element size in bits.
Definition at line 17448 of file X86ISelLowering.cpp.
References llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), getZeroVector(), llvm::X86Subtarget::hasInt256(), isSplatVector(), llvm::APInt::trunc(), llvm::APInt::uge(), llvm::MVT::v16i16, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8i16, and llvm::MVT::v8i32.
Referenced by PerformShiftCombine().
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Definition at line 17402 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::Constant, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), isSplatVector(), llvm::EVT::isVector(), llvm::X86ISD::SETCC_CARRY, llvm::APInt::shl(), and llvm::ISD::ZERO_EXTEND.
Referenced by PerformShiftCombine().
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PerformShuffleCombine - Performs several different shuffle combines.
Definition at line 16223 of file X86ISelLowering.cpp.
References EltsFromConsecutiveLoads(), llvm::SDNode::getOpcode(), getShuffleScalarElt(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasFp256(), llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLoweringBase::isTypeLegal(), PerformShuffleCombine256(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ISD::VECTOR_SHUFFLE.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
Definition at line 16127 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), getZeroVector(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::hasNUsesOfValue(), Insert128BitVector(), llvm::ISD::isBuildVectorAllZeros(), isShuffleHigh128VectorInsertLow(), isShuffleLow128VectorInsertHigh(), isUndefOrEqual(), N, llvm::MVT::Other, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::TokenFactor, llvm::ISD::UNDEF, llvm::SelectionDAG::UpdateNodeOperands(), llvm::MVT::v4i64, and llvm::X86ISD::VZEXT_LOAD.
Referenced by PerformShuffleCombine().
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Definition at line 18705 of file X86ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasInt256(), llvm::ISD::isNormalLoad(), llvm::EVT::isVector(), llvm::ISD::LOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::v4i32, and llvm::MVT::v4i64.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18936 of file X86ISelLowering.cpp.
References llvm::X86TargetLowering::BuildFILD(), llvm::MemSDNode::getChain(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::X86TargetLowering::getSubtarget(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::ISD::isNON_EXTLoad(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), llvm::ISD::LOAD, P, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8i32, and llvm::MVT::v8i8.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformSTORECombine - Do target-specific dag combines on STORE nodes.
Definition at line 18222 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, Extract128BitVector(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::MVT::FIRST_INTEGER_VALUETYPE, llvm::MemSDNode::getAlignment(), llvm::Function::getAttributes(), llvm::LoadSDNode::getBasePtr(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarType(), llvm::MVT::getSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::X86Subtarget::hasInt256(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::MemSDNode::isInvariant(), llvm::MemSDNode::isNonTemporal(), llvm::ISD::isNormalLoad(), llvm::isPowerOf2_32(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::MemSDNode::isVolatile(), llvm::MVT::LAST_INTEGER_VALUETYPE, llvm::MinAlign(), N, llvm::Attribute::NoImplicitFloat, llvm::TargetMachine::Options, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::TokenFactor, and llvm::TargetOptions::UseSoftFloat.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 19048 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasInt256(), llvm::SDNode::hasOneUse(), llvm::X86Subtarget::hasSSSE3(), llvm::X86ISD::HSUB, isHorizontalBinOp(), OptimizeConditionalInDecrement(), llvm::MVT::v16i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::ISD::XOR.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PerformTruncateCombine - Converts truncate operation to a sequence of vector shuffle operations. It is possible when we truncate 256-bit vector to 128-bit vector
Definition at line 16256 of file X86ISelLowering.cpp.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18692 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), and llvm::X86ISD::VZEXT_LOAD.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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performVZEXTCombine - Performs build vector combines
Definition at line 19082 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and llvm::X86ISD::VZEXT.
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 17987 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::X86ISD::BLSMSK, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::X86Subtarget::hasBMI(), llvm::X86Subtarget::hasCMov(), llvm::MVT::i32, llvm::MVT::i64, isAllOnes(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and performIntegerAbsCombine().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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Definition at line 18799 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::EVT::is256BitVector(), llvm::X86ISD::SETCC_CARRY, and WidenMaskArithmetic().
Referenced by llvm::X86TargetLowering::PerformDAGCombine().
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PromoteSplat - Splat is promoted to target supported vector shuffles.
Definition at line 4875 of file X86ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, Extract128BitVector(), getLegalSplat(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::i16, llvm::MVT::i8, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), and PromoteSplati8i16().
Referenced by LowerVECTOR_SHUFFLEv16i8(), and LowerVECTOR_SHUFFLEv8i16().
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Definition at line 4831 of file X86ISelLowering.cpp.
References llvm::SDValue::getSimpleValueType(), getUnpackh(), getUnpackl(), and llvm::MVT::getVectorNumElements().
Referenced by PromoteSplat().
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Definition at line 13483 of file X86ISelLowering.cpp.
References llvm::array_lengthof(), llvm::ISD::BUILD_PAIR, llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::Other, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::X86TargetLowering::ReplaceNodeResults().
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Definition at line 13461 of file X86ISelLowering.cpp.
References llvm::ISD::ATOMIC_CMP_SWAP, llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::X86TargetLowering::ReplaceNodeResults().
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RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be done when every pair / quad of shuffle mask elements point to elements in the right sequence. e.g. vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
Definition at line 6662 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MVT::SimpleTy, llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MVT::v8i32.
Referenced by NormalizeVectorShuffle().
ShouldXformToMOVHLPS - Return true if the node should be transformed to match movhlps. The lower half elements should come from upper half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order).
Definition at line 4590 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), and isUndefOrEqual().
ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to match movlp{s|d}. The lower half elements should come from lower half of V1 (and in order), and the upper half elements should come from the upper half of V2 (and in order). And since V1 will become the source of the MOVLP, it must be either a vector load or a scalar load to vector.
Definition at line 4646 of file X86ISelLowering.cpp.
References llvm::MVT::getVectorNumElements(), llvm::MVT::is128BitVector(), llvm::ISD::isNON_EXTLoad(), isScalarLoadToVector(), isUndefOrEqual(), and WillBeConstantPoolLoad().
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TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 specific condition code, returning the condition code and the LHS/RHS of the comparison to make.
Definition at line 3421 of file X86ISelLowering.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_P, llvm::X86::COND_S, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), llvm::ISD::isNON_EXTLoad(), llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and std::swap().
Referenced by LowerINTRINSIC_WO_CHAIN().
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Definition at line 9759 of file X86ISelLowering.cpp.
References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and std::swap().
Referenced by LowerVSETCC().
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Definition at line 17606 of file X86ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::APInt::getAllOnesValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::is128BitVector(), llvm::EVT::is256BitVector(), llvm::TargetLoweringBase::isOperationLegalOrPromote(), isSplatVector(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::TRUNCATE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zext().
Referenced by PerformSExtCombine(), and PerformZExtCombine().
Definition at line 4620 of file X86ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), and llvm::ISD::UNDEF.
Referenced by ShouldXformToMOVLP().
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XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target specific shuffle of a load can be folded into a single element load. Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but shuffles have been customed lowered so we need to handle those here.
Definition at line 16266 of file X86ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getContext(), llvm::TargetLoweringBase::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), getTargetShuffleMask(), llvm::EVT::getTypeForEVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDNode::hasNUsesOfValue(), llvm::SDValue::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), isTargetShuffle(), llvm::MemSDNode::isVolatile(), and llvm::ISD::LOAD.
Referenced by PerformEXTRACT_VECTOR_ELTCombine().
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